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c41da167d2
All patches automatically rebased. Build system: x86_64 Build-tested: bcm2711/RPi4B, mt7622/RT3200 Run-tested: bcm2711/RPi4B, mt7622/RT3200 Signed-off-by: John Audia <graysky@archlinux.us>
76 lines
2.4 KiB
Diff
76 lines
2.4 KiB
Diff
From f1bbbb260a8016373adf239c716d2da90e6ced0b Mon Sep 17 00:00:00 2001
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From: Hayes Wang <hayeswang@realtek.com>
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Date: Fri, 16 Apr 2021 16:04:32 +0800
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Subject: [PATCH] r8152: set inter fram gap time depending on speed
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commit 5133bcc7481528e36fff0a3b056601efb704fb32 upstream.
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Set the maximum inter frame gap time (144ns) for speed 10M/half and
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100M/half. It improves the performance for those speeds. And, there
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is no effect for the other speeds.
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For 10M/half and 100M/half, the fast inter frame gap time let the
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device couldn't use the feature of the aggregation effectively,
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because the transfer would be completed fastly. Therefore, use the
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maximum value to improve the effect of the aggregation. However, you
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may not feel the improvement for fast CPUs, because they compensate
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for the effect of the aggregation.
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Signed-off-by: Hayes Wang <hayeswang@realtek.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/usb/r8152.c | 28 ++++++++++++++++++++++++++++
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1 file changed, 28 insertions(+)
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--- a/drivers/net/usb/r8152.c
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+++ b/drivers/net/usb/r8152.c
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@@ -249,6 +249,9 @@
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/* PLA_TCR1 */
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#define VERSION_MASK 0x7cf0
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+#define IFG_MASK (BIT(3) | BIT(9) | BIT(8))
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+#define IFG_144NS BIT(9)
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+#define IFG_96NS (BIT(9) | BIT(8))
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/* PLA_MTPS */
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#define MTPS_JUMBO (12 * 1024 / 64)
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@@ -2747,6 +2750,29 @@ static int rtl_stop_rx(struct r8152 *tp)
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return 0;
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}
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+static void rtl_set_ifg(struct r8152 *tp, u16 speed)
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+{
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+ u32 ocp_data;
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+
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+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
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+ ocp_data &= ~IFG_MASK;
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+ if ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) {
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+ ocp_data |= IFG_144NS;
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+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
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+
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+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
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+ ocp_data &= ~TX10MIDLE_EN;
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+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
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+ } else {
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+ ocp_data |= IFG_96NS;
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+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
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+
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+ ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
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+ ocp_data |= TX10MIDLE_EN;
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+ ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
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+ }
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+}
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+
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static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
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{
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ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
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@@ -2850,6 +2876,8 @@ static int rtl8153_enable(struct r8152 *
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r8153_set_rx_early_timeout(tp);
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r8153_set_rx_early_size(tp);
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+ rtl_set_ifg(tp, rtl8152_get_speed(tp));
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+
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if (tp->version == RTL_VER_09) {
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u32 ocp_data;
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