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247043c968
Without this patch, when using rev 3 of the Atheros AR9344 SoC, the
gigabit switch (AR8327) does not work or works very erratically.
This is a re-spin of http://patchwork.ozlabs.org/patch/419857/ with a
different PLL value, according to the feedback from several users
(including myself) as shown here:
https://openwrt.org/toh/mikrotik/rb2011uias#tracking_reported_experience_with_suggested_patch_for_the_5_gige_ports
Performance is acceptable: testing L3 forwarding without NAT yields a
performance of 370 Mbit/s (iperf3 TCP) and 41 Kpps (iperf3 UDP with 64
bytes payload). Both tests show that 100% of CPU time is spent on softirq.
A similar fix for a different device (RB2011) was added in e457d22261
("Make GBit switch work on RB2011").
Signed-off-by: Baptiste Jonglez <git@bitsofnetworks.org>
328 lines
7.0 KiB
C
328 lines
7.0 KiB
C
/*
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* MikroTik RouterBOARD 95X support
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*
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* Copyright (C) 2012 Stijn Tintel <stijn@linux-ipv6.be>
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* Copyright (C) 2012 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2013 Kamil Trzcinski <ayufan@ayufan.eu>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#define pr_fmt(fmt) "rb95x: " fmt
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#include <linux/version.h>
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#include <linux/phy.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <linux/ath9k_platform.h>
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#include <linux/ar8216_platform.h>
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#include <linux/mtd/mtd.h>
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#if LINUX_VERSION_CODE < KERNEL_VERSION(4,14,0)
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#include <linux/mtd/nand.h>
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#else
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#include <linux/mtd/rawnand.h>
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#endif
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#include <linux/mtd/partitions.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/flash.h>
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#include <linux/routerboot.h>
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#include <linux/gpio.h>
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#include <linux/version.h>
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "common.h"
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#include "dev-eth.h"
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#include "dev-m25p80.h"
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#include "dev-nfc.h"
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#include "dev-usb.h"
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#include "dev-wmac.h"
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#include "machtypes.h"
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#include "routerboot.h"
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#include "dev-leds-gpio.h"
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#define RB95X_GPIO_NAND_NCE 14
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static struct mtd_partition rb95x_nand_partitions[] = {
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{
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.name = "booter",
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.offset = 0,
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.size = (256 * 1024),
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.mask_flags = MTD_WRITEABLE,
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},
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{
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.name = "kernel",
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.offset = (256 * 1024),
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.size = (4 * 1024 * 1024) - (256 * 1024),
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},
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{
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.name = "ubi",
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.offset = MTDPART_OFS_NXTBLK,
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.size = MTDPART_SIZ_FULL,
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},
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};
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static struct gpio_led rb951ui_leds_gpio[] __initdata = {
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{
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.name = "rb:green:wlan",
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.gpio = 11,
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.active_low = 1,
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}, {
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.name = "rb:green:act",
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.gpio = 3,
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.active_low = 1,
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}, {
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.name = "rb:green:port1",
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.gpio = 13,
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.active_low = 1,
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}, {
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.name = "rb:green:port2",
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.gpio = 12,
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.active_low = 1,
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}, {
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.name = "rb:green:port3",
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.gpio = 4,
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.active_low = 1,
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}, {
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.name = "rb:green:port4",
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.gpio = 21,
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.active_low = 1,
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}, {
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.name = "rb:green:port5",
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.gpio = 16,
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.active_low = 1,
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}
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};
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static struct ar8327_pad_cfg rb95x_ar8327_pad0_cfg = {
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.mode = AR8327_PAD_MAC_RGMII,
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.txclk_delay_en = true,
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.rxclk_delay_en = true,
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.txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
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.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
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};
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static struct ar8327_platform_data rb95x_ar8327_data = {
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.pad0_cfg = &rb95x_ar8327_pad0_cfg,
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.port0_cfg = {
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.force_link = 1,
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.speed = AR8327_PORT_SPEED_1000,
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.duplex = 1,
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.txpause = 1,
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.rxpause = 1,
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}
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};
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static struct mdio_board_info rb95x_mdio0_info[] = {
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{
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.bus_id = "ag71xx-mdio.0",
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.mdio_addr = 0,
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.platform_data = &rb95x_ar8327_data,
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},
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};
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void __init rb95x_wlan_init(void)
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{
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char *art_buf;
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u8 wlan_mac[ETH_ALEN];
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art_buf = rb_get_wlan_data();
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if (art_buf == NULL)
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return;
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ath79_init_mac(wlan_mac, ath79_mac_base, 11);
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ath79_register_wmac(art_buf + 0x1000, wlan_mac);
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kfree(art_buf);
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}
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static void rb95x_nand_select_chip(int chip_no)
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{
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switch (chip_no) {
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case 0:
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gpio_set_value(RB95X_GPIO_NAND_NCE, 0);
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break;
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default:
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gpio_set_value(RB95X_GPIO_NAND_NCE, 1);
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break;
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}
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ndelay(500);
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}
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#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
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static struct nand_ecclayout rb95x_nand_ecclayout = {
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.eccbytes = 6,
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.eccpos = { 8, 9, 10, 13, 14, 15 },
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.oobavail = 9,
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.oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
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};
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#else
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static int rb95x_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *oobregion)
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{
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switch (section) {
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case 0:
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oobregion->offset = 8;
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oobregion->length = 3;
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return 0;
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case 1:
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oobregion->offset = 13;
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oobregion->length = 3;
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return 0;
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default:
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return -ERANGE;
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}
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}
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static int rb95x_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *oobregion)
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{
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switch (section) {
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case 0:
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oobregion->offset = 0;
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oobregion->length = 4;
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return 0;
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case 1:
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oobregion->offset = 4;
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oobregion->length = 1;
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return 0;
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case 2:
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oobregion->offset = 6;
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oobregion->length = 2;
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return 0;
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case 3:
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oobregion->offset = 11;
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oobregion->length = 2;
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return 0;
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default:
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return -ERANGE;
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}
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}
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static const struct mtd_ooblayout_ops rb95x_nand_ecclayout_ops = {
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.ecc = rb95x_ooblayout_ecc,
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.free = rb95x_ooblayout_free,
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};
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#endif /* < 4.6 */
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static int rb95x_nand_scan_fixup(struct mtd_info *mtd)
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{
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#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
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struct nand_chip *chip = mtd->priv;
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#else
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struct nand_chip *chip = mtd_to_nand(mtd);
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#endif /* < 4.6.0 */
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if (mtd->writesize == 512) {
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/*
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* Use the OLD Yaffs-1 OOB layout, otherwise RouterBoot
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* will not be able to find the kernel that we load.
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*/
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#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
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chip->ecc.layout = &rb95x_nand_ecclayout;
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#else
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mtd_set_ooblayout(mtd, &rb95x_nand_ecclayout_ops);
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#endif
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}
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chip->options = NAND_NO_SUBPAGE_WRITE;
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return 0;
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}
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void __init rb95x_nand_init(void)
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{
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gpio_request_one(RB95X_GPIO_NAND_NCE, GPIOF_OUT_INIT_HIGH, "NAND nCE");
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ath79_nfc_set_scan_fixup(rb95x_nand_scan_fixup);
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ath79_nfc_set_parts(rb95x_nand_partitions,
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ARRAY_SIZE(rb95x_nand_partitions));
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ath79_nfc_set_select_chip(rb95x_nand_select_chip);
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ath79_nfc_set_swap_dma(true);
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ath79_register_nfc();
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}
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static int __init rb95x_setup(void)
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{
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const struct rb_info *info;
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info = rb_init_info((void *)(KSEG1ADDR(AR71XX_SPI_BASE)), 0x10000);
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if (!info)
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return -EINVAL;
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rb95x_nand_init();
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return 0;
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}
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static void __init rb951g_setup(void)
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{
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if (rb95x_setup())
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return;
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ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
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AR934X_ETH_CFG_RXD_DELAY |
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AR934X_ETH_CFG_SW_ONLY_MODE);
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ath79_register_mdio(0, 0x0);
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mdiobus_register_board_info(rb95x_mdio0_info,
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ARRAY_SIZE(rb95x_mdio0_info));
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ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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ath79_eth0_data.phy_mask = BIT(0);
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ath79_eth0_pll_data.pll_1000 = 0x6f000000;
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ath79_register_eth(0);
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rb95x_wlan_init();
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ath79_register_usb();
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}
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MIPS_MACHINE(ATH79_MACH_RB_951G, "951G", "MikroTik RouterBOARD 951G-2HnD",
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rb951g_setup);
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static void __init rb951ui_setup(void)
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{
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if (rb95x_setup())
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return;
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ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
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ath79_register_mdio(1, 0x0);
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ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
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ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
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ath79_switch_data.phy4_mii_en = 1;
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ath79_switch_data.phy_poll_mask = BIT(4);
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
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ath79_eth0_data.phy_mask = BIT(4);
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ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
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ath79_register_eth(0);
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ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
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ath79_register_eth(1);
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gpio_request_one(20, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
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"USB power");
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gpio_request_one(2, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
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"POE power");
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rb95x_wlan_init();
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ath79_register_usb();
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ath79_register_leds_gpio(-1, ARRAY_SIZE(rb951ui_leds_gpio),
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rb951ui_leds_gpio);
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}
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MIPS_MACHINE(ATH79_MACH_RB_951U, "951HnD", "MikroTik RouterBOARD 951Ui-2HnD",
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rb951ui_setup);
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