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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
22 lines
640 B
Diff
22 lines
640 B
Diff
From a22e1110a6ffcc2cf4b3b598f037879cbd0915d3 Mon Sep 17 00:00:00 2001
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From: Emil Renner Berthing <kernel@esmil.dk>
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Date: Wed, 31 Aug 2022 22:54:07 +0200
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Subject: [PATCH 1005/1024] RISC-V: Mark StarFive JH7100 as having non-coherent
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DMAs
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Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
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---
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arch/riscv/boot/dts/starfive/jh7100.dtsi | 1 +
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1 file changed, 1 insertion(+)
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--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
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+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
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@@ -111,6 +111,7 @@
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&plic>;
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+ dma-noncoherent;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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