openwrt/target/linux/ath79/dts/ar9344_devolo_magic-2-wifi.dts
Adrian Schmutzler 3a4b751110 ath79: enable UART in SoC DTSI files
The uart node is enabled on all devices except one (GL-USB150 *).
Thus, let's not have a few hundred nodes to enable it, but do not
disable it in the first place.

Where the majority of devices is using it, also move the serial0
alias to the DTSI.

*) Since GL-USB150 even defines serial0 alias, the missing uart
   is probably just a mistake. Anyway, disable it for now so this
   patch stays cosmetic.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2021-02-24 02:53:53 +01:00

174 lines
2.8 KiB
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "ar9344.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Devolo Magic 2 Wifi";
compatible = "devolo,magic-2-wifi", "qca,ar9344";
aliases {
led-boot = &led_dlan_red;
led-failsafe = &led_dlan_red;
led-running = &led_dlan_white;
led-upgrade = &led_dlan_red;
};
leds {
compatible = "gpio-leds";
wlan {
label = "white:wlan";
gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
led_dlan_white: dlan_white {
label = "white:dlan";
gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
};
led_dlan_red: dlan_red {
label = "red:dlan";
gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
panic-indicator;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "Reset button";
linux,code = <KEY_RESTART>;
gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
wifi {
label = "WIFI button";
linux,code = <KEY_RFKILL>;
gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
debounce-interval = <60>;
};
dlan {
label = "DLAN button";
linux,code = <BTN_0>;
gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
};
};
&gpio {
wlan_power {
gpio-hog;
line-name = "WLAN power";
gpios = <&gpio 21 GPIO_ACTIVE_HIGH>;
output-high;
};
};
&spi {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
uboot: partition@0 {
label = "u-boot";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "u-boot-env";
reg = <0x40000 0x10000>;
read-only;
};
partition@50000 {
label = "Config1";
reg = <0x50000 0x10000>;
read-only;
};
partition@60000 {
label = "Config2";
reg = <0x60000 0x10000>;
read-only;
};
partition@70000 {
compatible = "denx,uimage";
label = "firmware";
reg = <0x70000 0xf80000>;
};
art: partition@ff0000 {
label = "art";
reg = <0xff0000 0x10000>;
read-only;
};
};
};
};
&ref {
clock-frequency = <40000000>;
};
&eth0 {
status = "okay";
pll-data = <0x02000000 0x00000101 0x00001616>;
mtd-mac-address = <&art 0x1002>;
mtd-mac-address-increment = <2>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
&wmac {
status = "okay";
mtd-cal-data = <&art 0x1000>;
};
&pcie {
status = "okay";
wifi@0,0 {
compatible = "qcom,ath10k";
reg = <0 0 0 0 0>;
};
};
&mdio0 {
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
phy-mode = "rgmii";
qca,ar8327-initvals = <
/* PORT0: RGMII, MAC0/6 exchage, tx_delay 01, No rx_delay */
0x04 0x06400000
0x08 0x00000000 /* PORT5 PAD MODE CTRL */
0x0c 0x00000000 /* PORT6 PAD MODE CTRL */
0x7c 0x0000007e /* PORT0_STATUS */
>;
};
};