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c7bc8a9a13
GMAC0 interface of AR9344 SOC in Wallys DR344 board is connected with AR8035, not with AR8327. Without this fix, GE interface doesn't work at all or shows high packet loss ratio. Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
164 lines
4.4 KiB
C
164 lines
4.4 KiB
C
/*
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* Wallys DR344 board support
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*
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* Copyright (c) 2011 Qualcomm Atheros
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* Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (c) 2015 Philippe Duchein <wireless-dev@duchein.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <linux/phy.h>
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#include <linux/platform_device.h>
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#include <linux/ath9k_platform.h>
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#include <linux/platform_data/phy-at803x.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "common.h"
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#include "pci.h"
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#include "dev-ap9x-pci.h"
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#include "dev-gpio-buttons.h"
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#include "dev-eth.h"
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#include "dev-usb.h"
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#include "dev-leds-gpio.h"
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#include "dev-m25p80.h"
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#include "dev-spi.h"
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#include "dev-wmac.h"
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#include "machtypes.h"
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#define DR344_GPIO_LED_SIG1 15
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#define DR344_GPIO_LED_SIG2 11
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#define DR344_GPIO_LED_SIG3 12
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#define DR344_GPIO_LED_SIG4 13
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#define DR344_GPIO_EXTERNAL_LNA0 18
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#define DR344_GPIO_EXTERNAL_LNA1 19
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#define DR344_GPIO_LED_STATUS 14
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#define DR344_GPIO_BTN_RESET 12
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#define DR344_KEYS_POLL_INTERVAL 20 /* msecs */
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#define DR344_KEYS_DEBOUNCE_INTERVAL (3 * DR344_KEYS_POLL_INTERVAL)
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#define DR344_MAC0_OFFSET 0
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#define DR344_MAC1_OFFSET 8
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#define DR344_WMAC_CALDATA_OFFSET 0x1000
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#define DR344_PCIE_CALDATA_OFFSET 0x5000
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static struct gpio_led dr344_leds_gpio[] __initdata = {
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{
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.name = "dr344:green:status",
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.gpio = DR344_GPIO_LED_STATUS,
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.active_low = 1,
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},
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{
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.name = "dr344:red:sig1",
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.gpio = DR344_GPIO_LED_SIG1,
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.active_low = 1,
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},
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{
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.name = "dr344:yellow:sig2",
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.gpio = DR344_GPIO_LED_SIG2,
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.active_low = 1,
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},
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{
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.name = "dr344:green:sig3",
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.gpio = DR344_GPIO_LED_SIG3,
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.active_low = 1,
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},
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{
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.name = "dr344:green:sig4",
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.gpio = DR344_GPIO_LED_SIG4,
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.active_low = 1,
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}
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};
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static struct gpio_keys_button dr344_gpio_keys[] __initdata = {
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{
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.desc = "reset",
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.type = EV_KEY,
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.code = KEY_RESTART,
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.debounce_interval = DR344_KEYS_DEBOUNCE_INTERVAL,
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.gpio = DR344_GPIO_BTN_RESET,
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.active_low = 1,
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},
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};
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static struct at803x_platform_data dr344_at803x_data = {
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.disable_smarteee = 1,
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.enable_rgmii_rx_delay = 1,
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.enable_rgmii_tx_delay = 1,
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};
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static struct mdio_board_info dr344_mdio0_info[] = {
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{
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.bus_id = "ag71xx-mdio.0",
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.phy_addr = 0,
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.platform_data = &dr344_at803x_data,
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},
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};
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static void __init dr344_setup(void)
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{
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u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
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u8 *mac = (u8 *) KSEG1ADDR(0x1f03f810);
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ath79_register_m25p80(NULL);
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ath79_register_leds_gpio(-1, ARRAY_SIZE(dr344_leds_gpio),
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dr344_leds_gpio);
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ath79_register_gpio_keys_polled(-1, DR344_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(dr344_gpio_keys),
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dr344_gpio_keys);
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ath79_register_usb();
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ath79_wmac_set_ext_lna_gpio(0, DR344_GPIO_EXTERNAL_LNA0);
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ath79_wmac_set_ext_lna_gpio(1, DR344_GPIO_EXTERNAL_LNA1);
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ath79_register_wmac(art + DR344_WMAC_CALDATA_OFFSET, NULL);
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ath79_register_pci();
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mdiobus_register_board_info(dr344_mdio0_info,
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ARRAY_SIZE(dr344_mdio0_info));
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ath79_register_mdio(1, 0x0);
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ath79_register_mdio(0, 0x0);
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ath79_init_mac(ath79_eth0_data.mac_addr, mac + DR344_MAC0_OFFSET, 0);
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ath79_init_mac(ath79_eth1_data.mac_addr, mac + DR344_MAC1_OFFSET, 0);
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ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
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AR934X_ETH_CFG_SW_ONLY_MODE);
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/* GMAC0 is connected to an AR8035 Gbps PHY */
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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ath79_eth0_data.phy_mask = BIT(0);
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ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
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ath79_eth0_pll_data.pll_1000 = 0x02000000;
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ath79_eth0_pll_data.pll_100 = 0x0101;
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ath79_eth0_pll_data.pll_10 = 0x1313;
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/* GMAC1 is connected to the internal switch */
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ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
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ath79_eth1_data.speed = SPEED_1000;
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ath79_eth1_data.duplex = DUPLEX_FULL;
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ath79_register_eth(0);
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ath79_register_eth(1);
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}
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MIPS_MACHINE(ATH79_MACH_DR344, "DR344", "Wallys DR344", dr344_setup);
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