mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-23 15:32:33 +00:00
3da861ccca
Refreshed all patches. The following patches were manually changed: * 610-netfilter_match_bypass_default_checks.patch * 611-netfilter_match_bypass_default_table.patch * 802-can-0002-can-rx-offload-fix-long-lines.patch * 802-can-0003-can-rx-offload-can_rx_offload_compare-fix-typo.patch * 802-can-0004-can-rx-offload-can_rx_offload_irq_offload_timestamp-.patch * 802-can-0005-can-rx-offload-can_rx_offload_reset-remove-no-op-fun.patch * 802-can-0006-can-rx-offload-Prepare-for-CAN-FD-support.patch * 802-can-0018-can-flexcan-use-struct-canfd_frame-for-CAN-classic-f.patch The can-dev.ko model was moved in the upstream kernel. Compile-tested on: x86/64, armvirt/64, ath79/generic Runtime-tested on: x86/64, armvirt/64, ath79/generic Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
575 lines
13 KiB
Diff
575 lines
13 KiB
Diff
From 278bacf54eabe391159cef3112f8e8bf0fa7b891 Mon Sep 17 00:00:00 2001
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From: Florinel Iordache <florinel.iordache@nxp.com>
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Date: Mon, 27 May 2019 15:57:05 +0300
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Subject: [PATCH] arm64: dts: fsl: remove backplane support
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Remove entire backplane support from device tree for all supported platforms
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Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
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---
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.../boot/dts/freescale/fsl-ls1046a-qds-sdk.dts | 4 -
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.../boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts | 34 --------
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arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 5 --
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arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts | 26 -------
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arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 46 -----------
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arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts | 58 --------------
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arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 90 ----------------------
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arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 60 ---------------
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arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 86 ---------------------
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.../boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi | 4 +-
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.../boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi | 4 +-
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11 files changed, 4 insertions(+), 413 deletions(-)
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
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@@ -259,10 +259,6 @@ pcie@3600000 {
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dma-coherent;
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};
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-&serdes1 {
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- dma-coherent;
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-};
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-
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&fsldpaa {
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dma-coherent;
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};
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
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@@ -100,36 +100,6 @@ pcie@3600000 {
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compatible = "fsl,fman", "simple-bus";
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};
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-&mdio9 {
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- pcsphy6: ethernet-phy@0 {
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- backplane-mode = "10gbase-kr";
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- compatible = "ethernet-phy-ieee802.3-c45";
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- reg = <0x0>;
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- fsl,lane-handle = <&serdes1>;
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- fsl,lane-reg = <0x8C0 0x40>; /* lane D */
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- };
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-};
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-
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-&mdio10 {
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- pcsphy7: ethernet-phy@0 {
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- backplane-mode = "10gbase-kr";
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- compatible = "ethernet-phy-ieee802.3-c45";
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- reg = <0x0>;
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- fsl,lane-handle = <&serdes1>;
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- fsl,lane-reg = <0x880 0x40>; /* lane C */
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- };
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-};
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-
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-/* Update MAC connections to backplane PHYs
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- * &mac9 {
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- * phy-handle = <&pcsphy6>;
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- *};
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- *
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- *&mac10 {
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- * phy-handle = <&pcsphy7>;
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- *};
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-*/
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-
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&clockgen {
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dma-coherent;
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};
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@@ -298,10 +268,6 @@ pcie@3600000 {
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dma-coherent;
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};
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-&serdes1 {
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- dma-coherent;
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-};
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-
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&fsldpaa {
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dma-coherent;
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};
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
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@@ -680,11 +680,6 @@
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<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
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};
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- serdes1: serdes@1ea0000 {
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- reg = <0x0 0x1ea0000 0 0x00002000>;
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- compatible = "fsl,serdes-10g";
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- };
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-
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pcie@3400000 {
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compatible = "fsl,ls1046a-pcie";
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reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
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@@ -170,29 +170,3 @@
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&sata {
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status = "okay";
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};
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-
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-&pcs_mdio1 {
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- pcs_phy1: ethernet-phy@0 {
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- backplane-mode = "10gbase-kr";
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- compatible = "ethernet-phy-ieee802.3-c45";
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- reg = <0x0>;
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- fsl,lane-handle = <&serdes1>;
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- fsl,lane-reg = <0x840 0x40>;/* lane B */
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- };
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-};
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-
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-&pcs_mdio2 {
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- pcs_phy2: ethernet-phy@0 {
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- backplane-mode = "10gbase-kr";
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- compatible = "ethernet-phy-ieee802.3-c45";
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- reg = <0x0>;
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- fsl,lane-handle = <&serdes1>;
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- fsl,lane-reg = <0x800 0x40>;/* lane A */
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- };
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-};
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-
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-/* Update DPMAC connections to backplane PHYs, under SerDes 0x1D_0xXX.
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- * &dpmac1 {
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- * phy-handle = <&pcs_phy1>;
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- * };
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- */
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
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@@ -183,12 +183,6 @@
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little-endian;
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};
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- serdes1: serdes@1ea0000 {
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- compatible = "fsl,serdes-10g";
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- reg = <0x0 0x1ea0000 0 0x00002000>;
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- little-endian;
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- };
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-
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tmu: tmu@1f80000 {
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compatible = "fsl,qoriq-tmu";
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reg = <0x0 0x1f80000 0x0 0x10000>;
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@@ -333,46 +327,6 @@
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#address-cells = <1>;
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#size-cells = <0>;
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- };
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-
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- pcs_mdio1: mdio@8c07000 {
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- compatible = "fsl,fman-memac-mdio";
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- reg = <0x0 0x8c07000 0x0 0x1000>;
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- device_type = "mdio";
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- little-endian;
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-
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- #address-cells = <1>;
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- #size-cells = <0>;
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- };
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-
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- pcs_mdio2: mdio@8c0b000 {
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- compatible = "fsl,fman-memac-mdio";
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- reg = <0x0 0x8c0b000 0x0 0x1000>;
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- device_type = "mdio";
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- little-endian;
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-
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- #address-cells = <1>;
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- #size-cells = <0>;
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- };
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-
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- pcs_mdio3: mdio@8c0f000 {
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- compatible = "fsl,fman-memac-mdio";
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- reg = <0x0 0x8c0f000 0x0 0x1000>;
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- device_type = "mdio";
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- little-endian;
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-
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- #address-cells = <1>;
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- #size-cells = <0>;
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- };
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-
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- pcs_mdio4: mdio@8c13000 {
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- compatible = "fsl,fman-memac-mdio";
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- reg = <0x0 0x8c13000 0x0 0x1000>;
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- device_type = "mdio";
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- little-endian;
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-
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- #address-cells = <1>;
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- #size-cells = <0>;
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};
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ifc: ifc@2240000 {
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--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
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@@ -71,64 +71,6 @@
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};
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};
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-&pcs_mdio1 {
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- pcs_phy1: ethernet-phy@0 {
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- backplane-mode = "10gbase-kr";
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- compatible = "ethernet-phy-ieee802.3-c45";
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- reg = <0x0>;
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- fsl,lane-handle = <&serdes1>;
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- fsl,lane-reg = <0x9C0 0x40>;/* lane H */
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- };
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-};
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-
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-&pcs_mdio2 {
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- pcs_phy2: ethernet-phy@0 {
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- backplane-mode = "10gbase-kr";
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- compatible = "ethernet-phy-ieee802.3-c45";
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- reg = <0x0>;
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- fsl,lane-handle = <&serdes1>;
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- fsl,lane-reg = <0x980 0x40>;/* lane G */
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- };
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-};
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-
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-&pcs_mdio3 {
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- pcs_phy3: ethernet-phy@0 {
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- backplane-mode = "10gbase-kr";
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- compatible = "ethernet-phy-ieee802.3-c45";
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- reg = <0x0>;
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- fsl,lane-handle = <&serdes1>;
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- fsl,lane-reg = <0x940 0x40>;/* lane F */
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- };
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-};
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-
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-&pcs_mdio4 {
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- pcs_phy4: ethernet-phy@0 {
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- backplane-mode = "10gbase-kr";
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- compatible = "ethernet-phy-ieee802.3-c45";
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- reg = <0x0>;
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- fsl,lane-handle = <&serdes1>;
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- fsl,lane-reg = <0x900 0x40>;/* lane E */
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- };
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-};
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-
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-/* Update DPMAC connections to backplane PHYs, under SerDes 0x2a_0xXX.
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- * &dpmac1 {
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- * phy-handle = <&pcs_phy1>;
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- * };
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- *
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- * &dpmac2 {
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- * phy-handle = <&pcs_phy2>;
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- * };
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- *
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- * &dpmac3 {
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- * phy-handle = <&pcs_phy3>;
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- * };
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- *
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- * &dpmac4 {
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- * phy-handle = <&pcs_phy4>;
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- * };
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- */
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-
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/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
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&dpmac9 {
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phy-handle = <&mdio0_phy12>;
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--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
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@@ -550,90 +550,6 @@
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#size-cells = <0>;
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};
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- pcs_mdio1: mdio@8c07000 {
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- compatible = "fsl,fman-memac-mdio";
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- reg = <0x0 0x8c07000 0x0 0x1000>;
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- device_type = "mdio";
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- little-endian;
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-
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- #address-cells = <1>;
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- #size-cells = <0>;
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- };
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-
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- pcs_mdio2: mdio@8c0b000 {
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- compatible = "fsl,fman-memac-mdio";
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- reg = <0x0 0x8c0b000 0x0 0x1000>;
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- device_type = "mdio";
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- little-endian;
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-
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- #address-cells = <1>;
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- #size-cells = <0>;
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- };
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-
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- pcs_mdio3: mdio@8c0f000 {
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- compatible = "fsl,fman-memac-mdio";
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- reg = <0x0 0x8c0f000 0x0 0x1000>;
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- device_type = "mdio";
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- little-endian;
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-
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- #address-cells = <1>;
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- #size-cells = <0>;
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- };
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-
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- pcs_mdio4: mdio@8c13000 {
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- compatible = "fsl,fman-memac-mdio";
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- reg = <0x0 0x8c13000 0x0 0x1000>;
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- device_type = "mdio";
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- little-endian;
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-
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- #address-cells = <1>;
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- #size-cells = <0>;
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- };
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-
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- pcs_mdio5: mdio@8c17000 {
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- status = "disabled";
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- compatible = "fsl,fman-memac-mdio";
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- reg = <0x0 0x8c17000 0x0 0x1000>;
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- device_type = "mdio";
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- little-endian;
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-
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- #address-cells = <1>;
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- #size-cells = <0>;
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- };
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-
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- pcs_mdio6: mdio@8c1b000 {
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- status = "disabled";
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- compatible = "fsl,fman-memac-mdio";
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- reg = <0x0 0x8c1b000 0x0 0x1000>;
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- device_type = "mdio";
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- little-endian;
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-
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- #address-cells = <1>;
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- #size-cells = <0>;
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- };
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-
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- pcs_mdio7: mdio@8c1f000 {
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- status = "disabled";
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- compatible = "fsl,fman-memac-mdio";
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- reg = <0x0 0x8c1f000 0x0 0x1000>;
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- device_type = "mdio";
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- little-endian;
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-
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- #address-cells = <1>;
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- #size-cells = <0>;
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- };
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-
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- pcs_mdio8: mdio@8c23000 {
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- status = "disabled";
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- compatible = "fsl,fman-memac-mdio";
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- reg = <0x0 0x8c23000 0x0 0x1000>;
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- device_type = "mdio";
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- little-endian;
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-
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- #address-cells = <1>;
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- #size-cells = <0>;
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- };
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-
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i2c0: i2c@2000000 {
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status = "disabled";
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compatible = "fsl,vf610-i2c", "fsl,ls208xa-vf610-i2c";
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@@ -835,12 +751,6 @@
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snps,host-vbus-glitches;
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};
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- serdes1: serdes@1ea0000 {
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- compatible = "fsl,serdes-10g";
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- reg = <0x0 0x1ea0000 0 0x00002000>;
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- little-endian;
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- };
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-
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ccn@4000000 {
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compatible = "arm,ccn-504";
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reg = <0x0 0x04000000 0x0 0x01000000>;
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--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
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@@ -316,46 +316,6 @@
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status = "okay";
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};
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-&pcs_mdio1 {
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- pcs_phy1: ethernet-phy@0 {
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- compatible = "ethernet-phy-ieee802.3-c45";
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- backplane-mode = "40gbase-kr";
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- reg = <0x0>;
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- fsl,lane-handle = <&serdes1>;
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- fsl,lane-reg = <0xF00 0xE00 0xD00 0xC00>; /* lanes H, G, F, E */
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- };
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-};
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-
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-&pcs_mdio2 {
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- pcs_phy2: ethernet-phy@0 {
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- compatible = "ethernet-phy-ieee802.3-c45";
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- backplane-mode = "40gbase-kr";
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- reg = <0x0>;
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- fsl,lane-handle = <&serdes1>;
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- fsl,lane-reg = <0xB00 0xA00 0x900 0x800>; /* lanes D, C, B, A */
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- };
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-};
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-
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-&pcs_mdio3 {
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- pcs_phy3: ethernet-phy@0 {
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- compatible = "ethernet-phy-ieee802.3-c45";
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- backplane-mode = "10gbase-kr";
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- reg = <0x0>;
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- fsl,lane-handle = <&serdes1>;
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- fsl,lane-reg = <0xF00 0x100>; /* lane H */
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- };
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-};
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-
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-&pcs_mdio4 {
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- pcs_phy4: ethernet-phy@0 {
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- compatible = "ethernet-phy-ieee802.3-c45";
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- backplane-mode = "10gbase-kr";
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- reg = <0x0>;
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- fsl,lane-handle = <&serdes1>;
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- fsl,lane-reg = <0xE00 0x100>; /* lane G */
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- };
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-};
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-
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&sata0 {
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status = "okay";
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};
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@@ -371,23 +331,3 @@
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&sata3 {
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status = "okay";
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};
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-
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-/* Update DPMAC connections to 40G backplane PHYs
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- * &dpmac1 {
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- * phy-handle = <&pcs_phy1>;
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- * };
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- *
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- * &dpmac2 {
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- * phy-handle = <&pcs_phy2>;
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- * };
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- */
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-
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-/* Update DPMAC connections to 10G backplane PHYs
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- * &dpmac3 {
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- * phy-handle = <&pcs_phy3>;
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- * };
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- *
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- * &dpmac4 {
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- * phy-handle = <&pcs_phy4>;
|
|
- * };
|
|
- */
|
|
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
|
|
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
|
|
@@ -500,92 +500,6 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
- pcs_mdio1: mdio@8c07000 {
|
|
- compatible = "fsl,fman-memac-mdio";
|
|
- reg = <0x0 0x8c07000 0x0 0x1000>;
|
|
- device_type = "mdio";
|
|
- little-endian;
|
|
-
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- };
|
|
-
|
|
- pcs_mdio2: mdio@8c0b000 {
|
|
- compatible = "fsl,fman-memac-mdio";
|
|
- reg = <0x0 0x8c0b000 0x0 0x1000>;
|
|
- device_type = "mdio";
|
|
- little-endian;
|
|
-
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- };
|
|
-
|
|
- pcs_mdio3: mdio@8c0f000 {
|
|
- compatible = "fsl,fman-memac-mdio";
|
|
- reg = <0x0 0x8c0f000 0x0 0x1000>;
|
|
- device_type = "mdio";
|
|
- little-endian;
|
|
-
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- };
|
|
-
|
|
- pcs_mdio4: mdio@8c13000 {
|
|
- compatible = "fsl,fman-memac-mdio";
|
|
- reg = <0x0 0x8c13000 0x0 0x1000>;
|
|
- device_type = "mdio";
|
|
- little-endian;
|
|
-
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- };
|
|
-
|
|
- pcs_mdio5: mdio@8c17000 {
|
|
- compatible = "fsl,fman-memac-mdio";
|
|
- reg = <0x0 0x8c17000 0x0 0x1000>;
|
|
- device_type = "mdio";
|
|
- little-endian;
|
|
-
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- };
|
|
-
|
|
- pcs_mdio6: mdio@8c1b000 {
|
|
- compatible = "fsl,fman-memac-mdio";
|
|
- reg = <0x0 0x8c1b000 0x0 0x1000>;
|
|
- device_type = "mdio";
|
|
- little-endian;
|
|
-
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- };
|
|
-
|
|
- pcs_mdio7: mdio@8c1f000 {
|
|
- compatible = "fsl,fman-memac-mdio";
|
|
- reg = <0x0 0x8c1f000 0x0 0x1000>;
|
|
- device_type = "mdio";
|
|
- little-endian;
|
|
-
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- };
|
|
-
|
|
- pcs_mdio8: mdio@8c23000 {
|
|
- compatible = "fsl,fman-memac-mdio";
|
|
- reg = <0x0 0x8c23000 0x0 0x1000>;
|
|
- device_type = "mdio";
|
|
- little-endian;
|
|
-
|
|
- #address-cells = <1>;
|
|
- #size-cells = <0>;
|
|
- };
|
|
-
|
|
- serdes1: serdes@1ea0000 {
|
|
- compatible = "fsl,serdes-28g";
|
|
- reg = <0x0 0x1ea0000 0 0x00002000>;
|
|
- little-endian;
|
|
- };
|
|
-
|
|
i2c0: i2c@2000000 {
|
|
compatible = "fsl,vf610-i2c";
|
|
#address-cells = <1>;
|
|
--- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
|
|
+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
|
|
@@ -22,7 +22,7 @@ fman@1a00000 {
|
|
fsl,qman-channel-id = <0x800>;
|
|
};
|
|
|
|
- mac9: ethernet@f0000 {
|
|
+ ethernet@f0000 {
|
|
cell-index = <0x8>;
|
|
compatible = "fsl,fman-memac";
|
|
reg = <0xf0000 0x1000>;
|
|
@@ -30,7 +30,7 @@ fman@1a00000 {
|
|
pcsphy-handle = <&pcsphy6>;
|
|
};
|
|
|
|
- mdio9: mdio@f1000 {
|
|
+ mdio@f1000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
|
--- a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
|
|
+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
|
|
@@ -22,7 +22,7 @@ fman@1a00000 {
|
|
fsl,qman-channel-id = <0x801>;
|
|
};
|
|
|
|
- mac10: ethernet@f2000 {
|
|
+ ethernet@f2000 {
|
|
cell-index = <0x9>;
|
|
compatible = "fsl,fman-memac";
|
|
reg = <0xf2000 0x1000>;
|
|
@@ -30,7 +30,7 @@ fman@1a00000 {
|
|
pcsphy-handle = <&pcsphy7>;
|
|
};
|
|
|
|
- mdio10: mdio@f3000 {
|
|
+ mdio@f3000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|