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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
41 lines
1.5 KiB
Diff
41 lines
1.5 KiB
Diff
From 790e1157753b4dcc9bad4521987fe09aa6657876 Mon Sep 17 00:00:00 2001
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From: Geert Uytterhoeven <geert@linux-m68k.org>
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Date: Thu, 25 Nov 2021 14:21:18 +0100
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Subject: [PATCH 1003/1024] riscv: dts: starfive: Group tuples in interrupt
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properties
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To improve human readability and enable automatic validation, the tuples
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in the various properties containing interrupt specifiers should be
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grouped.
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Fix this by grouping the tuples of "interrupts-extended" properties
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using angle brackets.
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Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
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---
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arch/riscv/boot/dts/starfive/jh7100.dtsi | 8 ++++----
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1 file changed, 4 insertions(+), 4 deletions(-)
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--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
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+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
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@@ -118,15 +118,15 @@
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clint: clint@2000000 {
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compatible = "starfive,jh7100-clint", "sifive,clint0";
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reg = <0x0 0x2000000 0x0 0x10000>;
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- interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
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- &cpu1_intc 3 &cpu1_intc 7>;
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+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
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+ <&cpu1_intc 3>, <&cpu1_intc 7>;
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};
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plic: interrupt-controller@c000000 {
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compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
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reg = <0x0 0xc000000 0x0 0x4000000>;
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- interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9
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- &cpu1_intc 11 &cpu1_intc 9>;
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+ interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
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+ <&cpu1_intc 11>, <&cpu1_intc 9>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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