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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
366 lines
12 KiB
Diff
366 lines
12 KiB
Diff
From f6fbb431f9e3ac5c9144edf05340db9a96dffa59 Mon Sep 17 00:00:00 2001
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From: Changhuang Liang <changhuang.liang@starfivetech.com>
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Date: Mon, 29 May 2023 05:15:02 -0700
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Subject: [PATCH 075/122] phy: starfive: Add mipi dphy rx support
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Add mipi dphy rx support for the StarFive JH7110 SoC. It is used to
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transfer CSI camera data.
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Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
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---
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drivers/phy/Kconfig | 1 +
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drivers/phy/Makefile | 1 +
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drivers/phy/starfive/Kconfig | 13 +
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drivers/phy/starfive/Makefile | 2 +
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drivers/phy/starfive/phy-starfive-dphy-rx.c | 301 ++++++++++++++++++++
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5 files changed, 318 insertions(+)
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create mode 100644 drivers/phy/starfive/Kconfig
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create mode 100644 drivers/phy/starfive/Makefile
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create mode 100644 drivers/phy/starfive/phy-starfive-dphy-rx.c
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--- a/drivers/phy/Kconfig
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+++ b/drivers/phy/Kconfig
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@@ -91,6 +91,7 @@ source "drivers/phy/rockchip/Kconfig"
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source "drivers/phy/samsung/Kconfig"
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source "drivers/phy/socionext/Kconfig"
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source "drivers/phy/st/Kconfig"
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+source "drivers/phy/starfive/Kconfig"
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source "drivers/phy/sunplus/Kconfig"
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source "drivers/phy/tegra/Kconfig"
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source "drivers/phy/ti/Kconfig"
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--- a/drivers/phy/Makefile
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+++ b/drivers/phy/Makefile
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@@ -31,6 +31,7 @@ obj-y += allwinner/ \
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samsung/ \
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socionext/ \
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st/ \
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+ starfive/ \
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sunplus/ \
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tegra/ \
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ti/ \
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--- /dev/null
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+++ b/drivers/phy/starfive/Kconfig
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@@ -0,0 +1,13 @@
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+# SPDX-License-Identifier: GPL-2.0-only
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+#
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+# Phy drivers for StarFive platforms
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+#
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+
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+config PHY_STARFIVE_DPHY_RX
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+ tristate "StarFive D-PHY RX Support"
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+ select GENERIC_PHY
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+ select GENERIC_PHY_MIPI_DPHY
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+ help
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+ Choose this option if you have a StarFive D-PHY in your
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+ system. If M is selected, the module will be called
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+ phy-starfive-dphy-rx.
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--- /dev/null
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+++ b/drivers/phy/starfive/Makefile
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@@ -0,0 +1,2 @@
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+# SPDX-License-Identifier: GPL-2.0
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+obj-$(CONFIG_PHY_STARFIVE_DPHY_RX) += phy-starfive-dphy-rx.o
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--- /dev/null
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+++ b/drivers/phy/starfive/phy-starfive-dphy-rx.c
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@@ -0,0 +1,301 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * DPHY driver for the StarFive JH7110 SoC
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+ *
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+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
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+ */
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+
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+#include <linux/bitfield.h>
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+#include <linux/bitops.h>
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+#include <linux/clk.h>
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+#include <linux/io.h>
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+#include <linux/module.h>
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+#include <linux/of.h>
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+#include <linux/of_device.h>
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+#include <linux/phy/phy.h>
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+#include <linux/platform_device.h>
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+#include <linux/pm_runtime.h>
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+#include <linux/reset.h>
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+
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+#define STF_DPHY_APBCFGSAIF_SYSCFG(x) (x)
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+
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+#define STF_DPHY_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_EN BIT(6)
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+#define STF_DPHY_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_IN GENMASK(12, 7)
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+#define STF_DPHY_DA_CDPHY_R100_CTRL1_2D1C_EFUSE_EN BIT(19)
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+#define STF_DPHY_DA_CDPHY_R100_CTRL1_2D1C_EFUSE_IN GENMASK(25, 20)
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+
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+#define STF_DPHY_DATA_BUS16_8 BIT(8)
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+#define STF_DPHY_DEBUG_MODE_SEL GENMASK(15, 9)
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+
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+#define STF_DPHY_ENABLE_CLK BIT(6)
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+#define STF_DPHY_ENABLE_CLK1 BIT(7)
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+#define STF_DPHY_ENABLE_LAN0 BIT(8)
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+#define STF_DPHY_ENABLE_LAN1 BIT(9)
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+#define STF_DPHY_ENABLE_LAN2 BIT(10)
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+#define STF_DPHY_ENABLE_LAN3 BIT(11)
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+#define STF_DPHY_GPI_EN GENMASK(17, 12)
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+#define STF_DPHY_HS_FREQ_CHANGE_CLK BIT(18)
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+#define STF_DPHY_HS_FREQ_CHANGE_CLK1 BIT(19)
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+#define STF_DPHY_LANE_SWAP_CLK GENMASK(22, 20)
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+#define STF_DPHY_LANE_SWAP_CLK1 GENMASK(25, 23)
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+#define STF_DPHY_LANE_SWAP_LAN0 GENMASK(28, 26)
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+#define STF_DPHY_LANE_SWAP_LAN1 GENMASK(31, 29)
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+
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+#define STF_DPHY_LANE_SWAP_LAN2 GENMASK(2, 0)
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+#define STF_DPHY_LANE_SWAP_LAN3 GENMASK(5, 3)
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+#define STF_DPHY_MP_TEST_EN BIT(6)
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+#define STF_DPHY_MP_TEST_MODE_SEL GENMASK(11, 7)
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+#define STF_DPHY_PLL_CLK_SEL GENMASK(21, 12)
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+#define STF_DPHY_PRECOUNTER_IN_CLK GENMASK(29, 22)
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+
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+#define STF_DPHY_PRECOUNTER_IN_CLK1 GENMASK(7, 0)
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+#define STF_DPHY_PRECOUNTER_IN_LAN0 GENMASK(15, 8)
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+#define STF_DPHY_PRECOUNTER_IN_LAN1 GENMASK(23, 16)
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+#define STF_DPHY_PRECOUNTER_IN_LAN2 GENMASK(31, 24)
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+
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+#define STF_DPHY_PRECOUNTER_IN_LAN3 GENMASK(7, 0)
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+#define STF_DPHY_RX_1C2C_SEL BIT(8)
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+
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+#define STF_MAP_LANES_NUM 6
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+
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+struct regval {
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+ u32 addr;
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+ u32 val;
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+};
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+
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+struct stf_dphy_info {
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+ /**
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+ * @maps:
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+ *
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+ * Physical lanes and logic lanes mapping table.
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+ *
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+ * The default order is:
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+ * [clk lane0, data lane 0, data lane 1, data lane 2, date lane 3, clk lane 1]
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+ */
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+ u8 maps[STF_MAP_LANES_NUM];
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+};
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+
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+struct stf_dphy {
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+ struct device *dev;
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+ void __iomem *regs;
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+ struct clk *cfg_clk;
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+ struct clk *ref_clk;
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+ struct clk *tx_clk;
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+ struct reset_control *rstc;
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+ struct regulator *mipi_0p9;
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+ struct phy *phy;
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+ const struct stf_dphy_info *info;
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+};
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+
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+static const struct regval stf_dphy_init_list[] = {
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(4), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(8), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(12), 0x0000fff0 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(16), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(20), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(24), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(28), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(32), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(36), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(40), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(40), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(48), 0x24000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(52), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(56), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(60), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(64), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(68), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(72), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(76), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(80), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(84), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(88), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(92), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(96), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(100), 0x02000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(104), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(108), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(112), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(116), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(120), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(124), 0x0000000c },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(128), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(132), 0xcc500000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(136), 0x000000cc },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(140), 0x00000000 },
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+ { STF_DPHY_APBCFGSAIF_SYSCFG(144), 0x00000000 },
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+};
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+
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+static int stf_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
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+{
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+ struct stf_dphy *dphy = phy_get_drvdata(phy);
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+ const struct stf_dphy_info *info = dphy->info;
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+ int i;
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+
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+ for (i = 0; i < ARRAY_SIZE(stf_dphy_init_list); i++)
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+ writel(stf_dphy_init_list[i].val,
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+ dphy->regs + stf_dphy_init_list[i].addr);
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+
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+ writel(FIELD_PREP(STF_DPHY_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_EN, 1) |
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+ FIELD_PREP(STF_DPHY_DA_CDPHY_R100_CTRL0_2D1C_EFUSE_IN, 0x1b) |
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+ FIELD_PREP(STF_DPHY_DA_CDPHY_R100_CTRL1_2D1C_EFUSE_EN, 1) |
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+ FIELD_PREP(STF_DPHY_DA_CDPHY_R100_CTRL1_2D1C_EFUSE_IN, 0x1b),
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+ dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(0));
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+
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+ writel(FIELD_PREP(STF_DPHY_DATA_BUS16_8, 0) |
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+ FIELD_PREP(STF_DPHY_DEBUG_MODE_SEL, 0x5a),
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+ dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(184));
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+
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+ writel(FIELD_PREP(STF_DPHY_ENABLE_CLK, 1) |
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+ FIELD_PREP(STF_DPHY_ENABLE_CLK1, 1) |
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+ FIELD_PREP(STF_DPHY_ENABLE_LAN0, 1) |
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+ FIELD_PREP(STF_DPHY_ENABLE_LAN1, 1) |
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+ FIELD_PREP(STF_DPHY_ENABLE_LAN2, 1) |
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+ FIELD_PREP(STF_DPHY_ENABLE_LAN3, 1) |
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+ FIELD_PREP(STF_DPHY_GPI_EN, 0) |
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+ FIELD_PREP(STF_DPHY_HS_FREQ_CHANGE_CLK, 0) |
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+ FIELD_PREP(STF_DPHY_HS_FREQ_CHANGE_CLK1, 0) |
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+ FIELD_PREP(STF_DPHY_LANE_SWAP_CLK, info->maps[0]) |
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+ FIELD_PREP(STF_DPHY_LANE_SWAP_CLK1, info->maps[5]) |
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+ FIELD_PREP(STF_DPHY_LANE_SWAP_LAN0, info->maps[1]) |
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+ FIELD_PREP(STF_DPHY_LANE_SWAP_LAN1, info->maps[2]),
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+ dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(188));
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+
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+ writel(FIELD_PREP(STF_DPHY_LANE_SWAP_LAN2, info->maps[3]) |
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+ FIELD_PREP(STF_DPHY_LANE_SWAP_LAN3, info->maps[4]) |
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+ FIELD_PREP(STF_DPHY_MP_TEST_EN, 0) |
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+ FIELD_PREP(STF_DPHY_MP_TEST_MODE_SEL, 0) |
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+ FIELD_PREP(STF_DPHY_PLL_CLK_SEL, 0x37c) |
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+ FIELD_PREP(STF_DPHY_PRECOUNTER_IN_CLK, 8),
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+ dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(192));
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+
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+ writel(FIELD_PREP(STF_DPHY_PRECOUNTER_IN_CLK1, 8) |
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+ FIELD_PREP(STF_DPHY_PRECOUNTER_IN_LAN0, 7) |
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+ FIELD_PREP(STF_DPHY_PRECOUNTER_IN_LAN1, 7) |
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+ FIELD_PREP(STF_DPHY_PRECOUNTER_IN_LAN2, 7),
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+ dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(196));
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+
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+ writel(FIELD_PREP(STF_DPHY_PRECOUNTER_IN_LAN3, 7) |
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+ FIELD_PREP(STF_DPHY_RX_1C2C_SEL, 0),
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+ dphy->regs + STF_DPHY_APBCFGSAIF_SYSCFG(200));
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+
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+ return 0;
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+}
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+
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+static int stf_dphy_power_on(struct phy *phy)
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+{
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+ struct stf_dphy *dphy = phy_get_drvdata(phy);
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+ int ret;
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+
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+ pm_runtime_get_sync(dphy->dev);
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+
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+ ret = regulator_enable(dphy->mipi_0p9);
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+ if (ret)
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+ return ret;
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+
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+ clk_set_rate(dphy->cfg_clk, 99000000);
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+ clk_set_rate(dphy->ref_clk, 49500000);
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+ clk_set_rate(dphy->tx_clk, 19800000);
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+ reset_control_deassert(dphy->rstc);
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+
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+ return 0;
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+}
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+
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+static int stf_dphy_power_off(struct phy *phy)
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+{
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+ struct stf_dphy *dphy = phy_get_drvdata(phy);
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+
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+ reset_control_assert(dphy->rstc);
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+
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+ regulator_disable(dphy->mipi_0p9);
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+
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+ pm_runtime_put_sync(dphy->dev);
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+
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+ return 0;
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+}
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+
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+static const struct phy_ops stf_dphy_ops = {
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+ .configure = stf_dphy_configure,
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+ .power_on = stf_dphy_power_on,
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+ .power_off = stf_dphy_power_off,
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+};
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+
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+static int stf_dphy_probe(struct platform_device *pdev)
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+{
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+ struct phy_provider *phy_provider;
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+ struct stf_dphy *dphy;
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+
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+ dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL);
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+ if (!dphy)
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+ return -ENOMEM;
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+
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+ dphy->info = of_device_get_match_data(&pdev->dev);
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+
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+ dev_set_drvdata(&pdev->dev, dphy);
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+ dphy->dev = &pdev->dev;
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+
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+ dphy->regs = devm_platform_ioremap_resource(pdev, 0);
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+ if (IS_ERR(dphy->regs))
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+ return PTR_ERR(dphy->regs);
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+
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+ dphy->cfg_clk = devm_clk_get(&pdev->dev, "cfg");
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+ if (IS_ERR(dphy->cfg_clk))
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+ return PTR_ERR(dphy->cfg_clk);
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+
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+ dphy->ref_clk = devm_clk_get(&pdev->dev, "ref");
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+ if (IS_ERR(dphy->ref_clk))
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+ return PTR_ERR(dphy->ref_clk);
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+
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+ dphy->tx_clk = devm_clk_get(&pdev->dev, "tx");
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+ if (IS_ERR(dphy->tx_clk))
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+ return PTR_ERR(dphy->tx_clk);
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+
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+ dphy->rstc = devm_reset_control_array_get_exclusive(&pdev->dev);
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+ if (IS_ERR(dphy->rstc))
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+ return PTR_ERR(dphy->rstc);
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+
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+ dphy->mipi_0p9 = devm_regulator_get(&pdev->dev, "mipi_0p9");
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+ if (IS_ERR(dphy->mipi_0p9))
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+ return PTR_ERR(dphy->mipi_0p9);
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+
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+ dphy->phy = devm_phy_create(&pdev->dev, NULL, &stf_dphy_ops);
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+ if (IS_ERR(dphy->phy)) {
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+ dev_err(&pdev->dev, "Failed to create PHY\n");
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+ return PTR_ERR(dphy->phy);
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+ }
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+
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+ pm_runtime_enable(&pdev->dev);
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+
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+ phy_set_drvdata(dphy->phy, dphy);
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+ phy_provider = devm_of_phy_provider_register(&pdev->dev,
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+ of_phy_simple_xlate);
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+
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+ return PTR_ERR_OR_ZERO(phy_provider);
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+}
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+
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+static const struct stf_dphy_info starfive_dphy_info = {
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+ .maps = {4, 0, 1, 2, 3, 5},
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+};
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+
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+static const struct of_device_id stf_dphy_dt_ids[] = {
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+ {
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+ .compatible = "starfive,jh7110-dphy-rx",
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+ .data = &starfive_dphy_info,
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+ },
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+ { /* sentinel */ },
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+};
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+MODULE_DEVICE_TABLE(of, stf_dphy_dt_ids);
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+
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+static struct platform_driver stf_dphy_driver = {
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+ .probe = stf_dphy_probe,
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+ .driver = {
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+ .name = "starfive-dphy-rx",
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+ .of_match_table = stf_dphy_dt_ids,
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+ },
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+};
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+module_platform_driver(stf_dphy_driver);
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+
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+MODULE_AUTHOR("Jack Zhu <jack.zhu@starfivetech.com>");
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+MODULE_AUTHOR("Changhuang Liang <changhuang.liang@starfivetech.com>");
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+MODULE_DESCRIPTION("StarFive DPHY RX driver");
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+MODULE_LICENSE("GPL");
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