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8a9273d51e
Copy backport, hack, pending patch and config from 6.1 to 6.6. Signed-off-by: Weijie Gao <hackpascal@gmail.com>
244 lines
6.4 KiB
Diff
244 lines
6.4 KiB
Diff
From 6fb760972c49490b03f3db2ad64cf30bdd28c54a Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Mon, 29 Jan 2024 15:15:20 +0100
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Subject: [PATCH 2/5] net: phy: qcom: create and move functions to shared
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library
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Create and move functions to shared library in preparation for qca83xx
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PHY Family to be detached from at803x driver.
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Only the shared defines are moved to the shared qcom.h header.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Link: https://lore.kernel.org/r/20240129141600.2592-3-ansuelsmth@gmail.com
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/phy/qcom/Kconfig | 4 ++
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drivers/net/phy/qcom/Makefile | 1 +
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drivers/net/phy/qcom/at803x.c | 69 +----------------------------
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drivers/net/phy/qcom/qcom-phy-lib.c | 53 ++++++++++++++++++++++
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drivers/net/phy/qcom/qcom.h | 34 ++++++++++++++
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5 files changed, 94 insertions(+), 67 deletions(-)
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create mode 100644 drivers/net/phy/qcom/qcom-phy-lib.c
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create mode 100644 drivers/net/phy/qcom/qcom.h
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--- a/drivers/net/phy/qcom/Kconfig
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+++ b/drivers/net/phy/qcom/Kconfig
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@@ -1,6 +1,10 @@
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# SPDX-License-Identifier: GPL-2.0-only
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+config QCOM_NET_PHYLIB
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+ tristate
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+
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config AT803X_PHY
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tristate "Qualcomm Atheros AR803X PHYs and QCA833x PHYs"
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+ select QCOM_NET_PHYLIB
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depends on REGULATOR
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help
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Currently supports the AR8030, AR8031, AR8033, AR8035 and internal
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--- a/drivers/net/phy/qcom/Makefile
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+++ b/drivers/net/phy/qcom/Makefile
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@@ -1,2 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0
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+obj-$(CONFIG_QCOM_NET_PHYLIB) += qcom-phy-lib.o
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obj-$(CONFIG_AT803X_PHY) += at803x.o
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--- a/drivers/net/phy/qcom/at803x.c
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+++ b/drivers/net/phy/qcom/at803x.c
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@@ -22,6 +22,8 @@
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#include <linux/sfp.h>
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#include <dt-bindings/net/qca-ar803x.h>
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+#include "qcom.h"
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+
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#define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10
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#define AT803X_SFC_ASSERT_CRS BIT(11)
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#define AT803X_SFC_FORCE_LINK BIT(10)
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@@ -84,9 +86,6 @@
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#define AT803X_REG_CHIP_CONFIG 0x1f
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#define AT803X_BT_BX_REG_SEL 0x8000
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-#define AT803X_DEBUG_ADDR 0x1D
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-#define AT803X_DEBUG_DATA 0x1E
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-
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#define AT803X_MODE_CFG_MASK 0x0F
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#define AT803X_MODE_CFG_BASET_RGMII 0x00
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#define AT803X_MODE_CFG_BASET_SGMII 0x01
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@@ -103,19 +102,6 @@
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#define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
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#define AT803X_PSSR_MR_AN_COMPLETE 0x0200
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-#define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00
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-#define QCA8327_DEBUG_MANU_CTRL_EN BIT(2)
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-#define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2)
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-#define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15)
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-
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-#define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05
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-#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
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-
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-#define AT803X_DEBUG_REG_HIB_CTRL 0x0b
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-#define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10)
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-#define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13)
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-#define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15)
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-
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#define AT803X_DEBUG_REG_3C 0x3C
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#define AT803X_DEBUG_REG_GREEN 0x3D
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@@ -393,18 +379,6 @@ MODULE_DESCRIPTION("Qualcomm Atheros AR8
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MODULE_AUTHOR("Matus Ujhelyi");
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MODULE_LICENSE("GPL");
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-enum stat_access_type {
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- PHY,
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- MMD
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-};
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-
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-struct at803x_hw_stat {
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- const char *string;
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- u8 reg;
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- u32 mask;
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- enum stat_access_type access_type;
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-};
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-
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static struct at803x_hw_stat qca83xx_hw_stats[] = {
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{ "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
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{ "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
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@@ -439,45 +413,6 @@ struct at803x_context {
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u16 led_control;
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};
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-static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
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-{
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- int ret;
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-
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- ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
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- if (ret < 0)
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- return ret;
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-
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- return phy_write(phydev, AT803X_DEBUG_DATA, data);
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-}
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-
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-static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
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-{
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- int ret;
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-
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- ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
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- if (ret < 0)
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- return ret;
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-
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- return phy_read(phydev, AT803X_DEBUG_DATA);
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-}
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-
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-static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
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- u16 clear, u16 set)
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-{
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- u16 val;
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- int ret;
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-
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- ret = at803x_debug_reg_read(phydev, reg);
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- if (ret < 0)
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- return ret;
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-
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- val = ret & 0xffff;
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- val &= ~clear;
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- val |= set;
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-
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- return phy_write(phydev, AT803X_DEBUG_DATA, val);
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-}
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-
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static int at803x_write_page(struct phy_device *phydev, int page)
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{
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int mask;
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--- /dev/null
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+++ b/drivers/net/phy/qcom/qcom-phy-lib.c
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@@ -0,0 +1,53 @@
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+// SPDX-License-Identifier: GPL-2.0
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+
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+#include <linux/phy.h>
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+#include <linux/module.h>
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+
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+#include "qcom.h"
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+
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+MODULE_DESCRIPTION("Qualcomm PHY driver Common Functions");
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+MODULE_AUTHOR("Matus Ujhelyi");
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+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
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+MODULE_LICENSE("GPL");
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+
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+int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
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+{
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+ int ret;
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+
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+ ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
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+ if (ret < 0)
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+ return ret;
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+
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+ return phy_read(phydev, AT803X_DEBUG_DATA);
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+}
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+EXPORT_SYMBOL_GPL(at803x_debug_reg_read);
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+
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+int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
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+ u16 clear, u16 set)
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+{
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+ u16 val;
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+ int ret;
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+
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+ ret = at803x_debug_reg_read(phydev, reg);
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+ if (ret < 0)
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+ return ret;
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+
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+ val = ret & 0xffff;
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+ val &= ~clear;
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+ val |= set;
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+
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+ return phy_write(phydev, AT803X_DEBUG_DATA, val);
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+}
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+EXPORT_SYMBOL_GPL(at803x_debug_reg_mask);
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+
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+int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
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+{
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+ int ret;
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+
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+ ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
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+ if (ret < 0)
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+ return ret;
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+
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+ return phy_write(phydev, AT803X_DEBUG_DATA, data);
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+}
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+EXPORT_SYMBOL_GPL(at803x_debug_reg_write);
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--- /dev/null
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+++ b/drivers/net/phy/qcom/qcom.h
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@@ -0,0 +1,34 @@
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+/* SPDX-License-Identifier: GPL-2.0 */
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+
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+#define AT803X_DEBUG_ADDR 0x1D
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+#define AT803X_DEBUG_DATA 0x1E
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+
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+#define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00
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+#define QCA8327_DEBUG_MANU_CTRL_EN BIT(2)
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+#define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2)
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+#define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15)
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+
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+#define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05
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+#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
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+
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+#define AT803X_DEBUG_REG_HIB_CTRL 0x0b
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+#define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10)
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+#define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13)
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+#define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15)
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+
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+enum stat_access_type {
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+ PHY,
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+ MMD
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+};
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+
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+struct at803x_hw_stat {
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+ const char *string;
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+ u8 reg;
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+ u32 mask;
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+ enum stat_access_type access_type;
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+};
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+
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+int at803x_debug_reg_read(struct phy_device *phydev, u16 reg);
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+int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
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+ u16 clear, u16 set);
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+int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data);
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