mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-20 22:23:27 +00:00
d6aea46a50
Refreshed all patches. Altered patches: - 902-debloat_proc.patch - 040-dmaengine-qcom-bam-Process-multiple-pending-descript.patch - 807-usb-support-layerscape.patch - 809-flexcan-support-layerscape.patch - 816-pcie-support-layerscape.patch Remove upstreamed: - 150-MIPS-bmips-mark-exception-vectors-as-char-arrays.patch - 303-spi-nor-enable-4B-opcodes-for-mx66l51235l.patch New symbols: X86_INTEL_MPX X86_INTEL_MEMORY_PROTECTION_KEYS X86_INTEL_TSX_MODE_OFF X86_INTEL_TSX_MODE_ON X86_INTEL_TSX_MODE_AUTO SGL_ALLOC Compile-tested on: cns3xxx, x86_64 Runtime-tested on: cns3xxx Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
597 lines
20 KiB
Diff
597 lines
20 KiB
Diff
From 3ed707fde8a33f2b888f75ac2f5e0a98e7774dad Mon Sep 17 00:00:00 2001
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From: Biwen Li <biwen.li@nxp.com>
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Date: Tue, 30 Oct 2018 18:26:27 +0800
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Subject: [PATCH 26/40] flexcan: support layerscape
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This is an integrated patch of flexcan for layerscape
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Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
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Signed-off-by: Guanhua Gao <guanhua.gao@nxp.com>
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Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
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Signed-off-by: Sakar Arora <Sakar.Arora@freescale.com>
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Signed-off-by: Biwen Li <biwen.li@nxp.com>
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---
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drivers/net/can/flexcan.c | 240 ++++++++++++++++++++++----------------
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1 file changed, 138 insertions(+), 102 deletions(-)
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--- a/drivers/net/can/flexcan.c
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+++ b/drivers/net/can/flexcan.c
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@@ -190,6 +190,7 @@
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* MX53 FlexCAN2 03.00.00.00 yes no no no no
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* MX6s FlexCAN3 10.00.12.00 yes yes no no yes
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* VF610 FlexCAN3 ? no yes no yes yes?
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+ * LS1021A FlexCAN2 03.00.04.00 no yes no yes
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*
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* Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
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*/
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@@ -279,6 +280,10 @@ struct flexcan_priv {
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struct clk *clk_per;
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const struct flexcan_devtype_data *devtype_data;
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struct regulator *reg_xceiver;
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+
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+ /* Read and Write APIs */
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+ u32 (*read)(void __iomem *addr);
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+ void (*write)(u32 val, void __iomem *addr);
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};
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static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
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@@ -301,6 +306,11 @@ static const struct flexcan_devtype_data
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FLEXCAN_QUIRK_BROKEN_PERR_STATE,
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};
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+static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
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+ .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
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+ FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_OFF_TIMESTAMP,
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+};
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+
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static const struct can_bittiming_const flexcan_bittiming_const = {
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.name = DRV_NAME,
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.tseg1_min = 4,
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@@ -313,39 +323,45 @@ static const struct can_bittiming_const
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.brp_inc = 1,
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};
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-/* Abstract off the read/write for arm versus ppc. This
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- * assumes that PPC uses big-endian registers and everything
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- * else uses little-endian registers, independent of CPU
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- * endianness.
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+/* FlexCAN module is essentially modelled as a little-endian IP in most
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+ * SoCs, i.e the registers as well as the message buffer areas are
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+ * implemented in a little-endian fashion.
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+ *
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+ * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
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+ * module in a big-endian fashion (i.e the registers as well as the
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+ * message buffer areas are implemented in a big-endian way).
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+ *
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+ * In addition, the FlexCAN module can be found on SoCs having ARM or
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+ * PPC cores. So, we need to abstract off the register read/write
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+ * functions, ensuring that these cater to all the combinations of module
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+ * endianness and underlying CPU endianness.
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*/
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-#if defined(CONFIG_PPC)
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-static inline u32 flexcan_read(void __iomem *addr)
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+static inline u32 flexcan_read_be(void __iomem *addr)
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{
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- return in_be32(addr);
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+ return ioread32be(addr);
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}
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-static inline void flexcan_write(u32 val, void __iomem *addr)
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+static inline void flexcan_write_be(u32 val, void __iomem *addr)
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{
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- out_be32(addr, val);
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+ iowrite32be(val, addr);
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}
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-#else
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-static inline u32 flexcan_read(void __iomem *addr)
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+
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+static inline u32 flexcan_read_le(void __iomem *addr)
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{
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- return readl(addr);
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+ return ioread32(addr);
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}
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-static inline void flexcan_write(u32 val, void __iomem *addr)
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+static inline void flexcan_write_le(u32 val, void __iomem *addr)
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{
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- writel(val, addr);
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+ iowrite32(val, addr);
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}
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-#endif
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static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv)
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{
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struct flexcan_regs __iomem *regs = priv->regs;
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u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK);
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- flexcan_write(reg_ctrl, ®s->ctrl);
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+ priv->write(reg_ctrl, ®s->ctrl);
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}
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static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv)
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@@ -353,7 +369,7 @@ static inline void flexcan_error_irq_dis
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struct flexcan_regs __iomem *regs = priv->regs;
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u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK);
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- flexcan_write(reg_ctrl, ®s->ctrl);
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+ priv->write(reg_ctrl, ®s->ctrl);
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}
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static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
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@@ -378,14 +394,14 @@ static int flexcan_chip_enable(struct fl
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unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
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u32 reg;
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- reg = flexcan_read(®s->mcr);
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+ reg = priv->read(®s->mcr);
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reg &= ~FLEXCAN_MCR_MDIS;
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- flexcan_write(reg, ®s->mcr);
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+ priv->write(reg, ®s->mcr);
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- while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
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+ while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
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udelay(10);
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- if (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
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+ if (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)
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return -ETIMEDOUT;
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return 0;
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@@ -397,14 +413,14 @@ static int flexcan_chip_disable(struct f
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unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
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u32 reg;
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- reg = flexcan_read(®s->mcr);
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+ reg = priv->read(®s->mcr);
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reg |= FLEXCAN_MCR_MDIS;
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- flexcan_write(reg, ®s->mcr);
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+ priv->write(reg, ®s->mcr);
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- while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
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+ while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
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udelay(10);
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- if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
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+ if (!(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK))
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return -ETIMEDOUT;
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return 0;
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@@ -416,14 +432,14 @@ static int flexcan_chip_freeze(struct fl
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unsigned int timeout = 1000 * 1000 * 10 / priv->can.bittiming.bitrate;
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u32 reg;
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- reg = flexcan_read(®s->mcr);
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+ reg = priv->read(®s->mcr);
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reg |= FLEXCAN_MCR_HALT;
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- flexcan_write(reg, ®s->mcr);
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+ priv->write(reg, ®s->mcr);
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- while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
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+ while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
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udelay(100);
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- if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
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+ if (!(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
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return -ETIMEDOUT;
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return 0;
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@@ -435,14 +451,14 @@ static int flexcan_chip_unfreeze(struct
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unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
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u32 reg;
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- reg = flexcan_read(®s->mcr);
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+ reg = priv->read(®s->mcr);
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reg &= ~FLEXCAN_MCR_HALT;
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- flexcan_write(reg, ®s->mcr);
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+ priv->write(reg, ®s->mcr);
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- while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
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+ while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK))
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udelay(10);
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- if (flexcan_read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
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+ if (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)
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return -ETIMEDOUT;
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return 0;
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@@ -453,11 +469,11 @@ static int flexcan_chip_softreset(struct
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struct flexcan_regs __iomem *regs = priv->regs;
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unsigned int timeout = FLEXCAN_TIMEOUT_US / 10;
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- flexcan_write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
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- while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
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+ priv->write(FLEXCAN_MCR_SOFTRST, ®s->mcr);
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+ while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST))
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udelay(10);
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- if (flexcan_read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
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+ if (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST)
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return -ETIMEDOUT;
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return 0;
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@@ -468,7 +484,7 @@ static int __flexcan_get_berr_counter(co
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{
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const struct flexcan_priv *priv = netdev_priv(dev);
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struct flexcan_regs __iomem *regs = priv->regs;
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- u32 reg = flexcan_read(®s->ecr);
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+ u32 reg = priv->read(®s->ecr);
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bec->txerr = (reg >> 0) & 0xff;
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bec->rxerr = (reg >> 8) & 0xff;
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@@ -524,24 +540,24 @@ static int flexcan_start_xmit(struct sk_
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if (cf->can_dlc > 0) {
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data = be32_to_cpup((__be32 *)&cf->data[0]);
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- flexcan_write(data, &priv->tx_mb->data[0]);
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+ priv->write(data, &priv->tx_mb->data[0]);
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}
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if (cf->can_dlc > 4) {
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data = be32_to_cpup((__be32 *)&cf->data[4]);
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- flexcan_write(data, &priv->tx_mb->data[1]);
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+ priv->write(data, &priv->tx_mb->data[1]);
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}
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can_put_echo_skb(skb, dev, 0);
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- flexcan_write(can_id, &priv->tx_mb->can_id);
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- flexcan_write(ctrl, &priv->tx_mb->can_ctrl);
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+ priv->write(can_id, &priv->tx_mb->can_id);
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+ priv->write(ctrl, &priv->tx_mb->can_ctrl);
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/* Errata ERR005829 step8:
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* Write twice INACTIVE(0x8) code to first MB.
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*/
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- flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
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+ priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
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&priv->tx_mb_reserved->can_ctrl);
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- flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
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+ priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
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&priv->tx_mb_reserved->can_ctrl);
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return NETDEV_TX_OK;
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@@ -660,7 +676,7 @@ static unsigned int flexcan_mailbox_read
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u32 code;
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do {
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- reg_ctrl = flexcan_read(&mb->can_ctrl);
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+ reg_ctrl = priv->read(&mb->can_ctrl);
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} while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT);
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/* is this MB empty? */
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@@ -675,17 +691,17 @@ static unsigned int flexcan_mailbox_read
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offload->dev->stats.rx_errors++;
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}
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} else {
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- reg_iflag1 = flexcan_read(®s->iflag1);
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+ reg_iflag1 = priv->read(®s->iflag1);
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if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE))
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return 0;
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- reg_ctrl = flexcan_read(&mb->can_ctrl);
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+ reg_ctrl = priv->read(&mb->can_ctrl);
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}
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/* increase timstamp to full 32 bit */
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*timestamp = reg_ctrl << 16;
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- reg_id = flexcan_read(&mb->can_id);
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+ reg_id = priv->read(&mb->can_id);
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if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
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cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
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else
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@@ -695,19 +711,19 @@ static unsigned int flexcan_mailbox_read
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cf->can_id |= CAN_RTR_FLAG;
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cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
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- *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
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- *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
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+ *(__be32 *)(cf->data + 0) = cpu_to_be32(priv->read(&mb->data[0]));
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+ *(__be32 *)(cf->data + 4) = cpu_to_be32(priv->read(&mb->data[1]));
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/* mark as read */
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if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
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/* Clear IRQ */
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if (n < 32)
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- flexcan_write(BIT(n), ®s->iflag1);
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+ priv->write(BIT(n), ®s->iflag1);
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else
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- flexcan_write(BIT(n - 32), ®s->iflag2);
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+ priv->write(BIT(n - 32), ®s->iflag2);
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} else {
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- flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
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- flexcan_read(®s->timer);
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+ priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1);
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+ priv->read(®s->timer);
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}
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return 1;
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@@ -719,8 +735,8 @@ static inline u64 flexcan_read_reg_iflag
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struct flexcan_regs __iomem *regs = priv->regs;
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u32 iflag1, iflag2;
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- iflag2 = flexcan_read(®s->iflag2) & priv->reg_imask2_default;
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- iflag1 = flexcan_read(®s->iflag1) & priv->reg_imask1_default &
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+ iflag2 = priv->read(®s->iflag2) & priv->reg_imask2_default;
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+ iflag1 = priv->read(®s->iflag1) & priv->reg_imask1_default &
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~FLEXCAN_IFLAG_MB(priv->tx_mb_idx);
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return (u64)iflag2 << 32 | iflag1;
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@@ -736,7 +752,7 @@ static irqreturn_t flexcan_irq(int irq,
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u32 reg_iflag1, reg_esr;
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enum can_state last_state = priv->can.state;
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- reg_iflag1 = flexcan_read(®s->iflag1);
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+ reg_iflag1 = priv->read(®s->iflag1);
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/* reception interrupt */
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if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
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@@ -759,7 +775,8 @@ static irqreturn_t flexcan_irq(int irq,
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/* FIFO overflow interrupt */
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if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
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handled = IRQ_HANDLED;
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- flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, ®s->iflag1);
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+ priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW,
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+ ®s->iflag1);
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dev->stats.rx_over_errors++;
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dev->stats.rx_errors++;
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}
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@@ -773,18 +790,18 @@ static irqreturn_t flexcan_irq(int irq,
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can_led_event(dev, CAN_LED_EVENT_TX);
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/* after sending a RTR frame MB is in RX mode */
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- flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
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- &priv->tx_mb->can_ctrl);
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- flexcan_write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), ®s->iflag1);
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+ priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
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+ &priv->tx_mb->can_ctrl);
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+ priv->write(FLEXCAN_IFLAG_MB(priv->tx_mb_idx), ®s->iflag1);
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netif_wake_queue(dev);
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}
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- reg_esr = flexcan_read(®s->esr);
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+ reg_esr = priv->read(®s->esr);
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/* ACK all bus error and state change IRQ sources */
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if (reg_esr & FLEXCAN_ESR_ALL_INT) {
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handled = IRQ_HANDLED;
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- flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr);
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+ priv->write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr);
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}
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/* state change interrupt or broken error state quirk fix is enabled */
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@@ -846,7 +863,7 @@ static void flexcan_set_bittiming(struct
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struct flexcan_regs __iomem *regs = priv->regs;
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u32 reg;
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- reg = flexcan_read(®s->ctrl);
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+ reg = priv->read(®s->ctrl);
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reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
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FLEXCAN_CTRL_RJW(0x3) |
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FLEXCAN_CTRL_PSEG1(0x7) |
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@@ -870,11 +887,11 @@ static void flexcan_set_bittiming(struct
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reg |= FLEXCAN_CTRL_SMP;
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netdev_dbg(dev, "writing ctrl=0x%08x\n", reg);
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- flexcan_write(reg, ®s->ctrl);
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+ priv->write(reg, ®s->ctrl);
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/* print chip status */
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netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
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- flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
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+ priv->read(®s->mcr), priv->read(®s->ctrl));
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}
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/* flexcan_chip_start
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@@ -913,7 +930,7 @@ static int flexcan_chip_start(struct net
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* choose format C
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* set max mailbox number
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*/
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- reg_mcr = flexcan_read(®s->mcr);
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+ reg_mcr = priv->read(®s->mcr);
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reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
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reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT | FLEXCAN_MCR_SUPV |
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FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_SRX_DIS | FLEXCAN_MCR_IRMQ |
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@@ -927,7 +944,7 @@ static int flexcan_chip_start(struct net
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FLEXCAN_MCR_MAXMB(priv->tx_mb_idx);
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}
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netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
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- flexcan_write(reg_mcr, ®s->mcr);
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+ priv->write(reg_mcr, ®s->mcr);
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/* CTRL
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*
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@@ -940,7 +957,7 @@ static int flexcan_chip_start(struct net
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* enable bus off interrupt
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* (== FLEXCAN_CTRL_ERR_STATE)
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*/
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- reg_ctrl = flexcan_read(®s->ctrl);
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+ reg_ctrl = priv->read(®s->ctrl);
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reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
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reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
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FLEXCAN_CTRL_ERR_STATE;
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@@ -960,45 +977,45 @@ static int flexcan_chip_start(struct net
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/* leave interrupts disabled for now */
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reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL;
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netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
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- flexcan_write(reg_ctrl, ®s->ctrl);
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+ priv->write(reg_ctrl, ®s->ctrl);
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if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
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- reg_ctrl2 = flexcan_read(®s->ctrl2);
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+ reg_ctrl2 = priv->read(®s->ctrl2);
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reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS;
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- flexcan_write(reg_ctrl2, ®s->ctrl2);
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+ priv->write(reg_ctrl2, ®s->ctrl2);
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}
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/* clear and invalidate all mailboxes first */
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for (i = priv->tx_mb_idx; i < ARRAY_SIZE(regs->mb); i++) {
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- flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
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- ®s->mb[i].can_ctrl);
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+ priv->write(FLEXCAN_MB_CODE_RX_INACTIVE,
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+ ®s->mb[i].can_ctrl);
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}
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if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
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for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++)
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- flexcan_write(FLEXCAN_MB_CODE_RX_EMPTY,
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- ®s->mb[i].can_ctrl);
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+ priv->write(FLEXCAN_MB_CODE_RX_EMPTY,
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+ ®s->mb[i].can_ctrl);
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}
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/* Errata ERR005829: mark first TX mailbox as INACTIVE */
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- flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
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- &priv->tx_mb_reserved->can_ctrl);
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+ priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
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+ &priv->tx_mb_reserved->can_ctrl);
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/* mark TX mailbox as INACTIVE */
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- flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
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- &priv->tx_mb->can_ctrl);
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+ priv->write(FLEXCAN_MB_CODE_TX_INACTIVE,
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+ &priv->tx_mb->can_ctrl);
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/* acceptance mask/acceptance code (accept everything) */
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- flexcan_write(0x0, ®s->rxgmask);
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- flexcan_write(0x0, ®s->rx14mask);
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- flexcan_write(0x0, ®s->rx15mask);
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+ priv->write(0x0, ®s->rxgmask);
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+ priv->write(0x0, ®s->rx14mask);
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+ priv->write(0x0, ®s->rx15mask);
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if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
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- flexcan_write(0x0, ®s->rxfgmask);
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+ priv->write(0x0, ®s->rxfgmask);
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/* clear acceptance filters */
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for (i = 0; i < ARRAY_SIZE(regs->mb); i++)
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- flexcan_write(0, ®s->rximr[i]);
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+ priv->write(0, ®s->rximr[i]);
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/* On Vybrid, disable memory error detection interrupts
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* and freeze mode.
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@@ -1011,17 +1028,17 @@ static int flexcan_chip_start(struct net
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* and Correction of Memory Errors" to write to
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* MECR register
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*/
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- reg_ctrl2 = flexcan_read(®s->ctrl2);
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+ reg_ctrl2 = priv->read(®s->ctrl2);
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reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
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- flexcan_write(reg_ctrl2, ®s->ctrl2);
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+ priv->write(reg_ctrl2, ®s->ctrl2);
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- reg_mecr = flexcan_read(®s->mecr);
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+ reg_mecr = priv->read(®s->mecr);
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reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
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- flexcan_write(reg_mecr, ®s->mecr);
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+ priv->write(reg_mecr, ®s->mecr);
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reg_mecr |= FLEXCAN_MECR_ECCDIS;
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reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
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FLEXCAN_MECR_FANCEI_MSK);
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- flexcan_write(reg_mecr, ®s->mecr);
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+ priv->write(reg_mecr, ®s->mecr);
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}
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err = flexcan_transceiver_enable(priv);
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@@ -1037,14 +1054,14 @@ static int flexcan_chip_start(struct net
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/* enable interrupts atomically */
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disable_irq(dev->irq);
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- flexcan_write(priv->reg_ctrl_default, ®s->ctrl);
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- flexcan_write(priv->reg_imask1_default, ®s->imask1);
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- flexcan_write(priv->reg_imask2_default, ®s->imask2);
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+ priv->write(priv->reg_ctrl_default, ®s->ctrl);
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+ priv->write(priv->reg_imask1_default, ®s->imask1);
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+ priv->write(priv->reg_imask2_default, ®s->imask2);
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enable_irq(dev->irq);
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/* print chip status */
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netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
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- flexcan_read(®s->mcr), flexcan_read(®s->ctrl));
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+ priv->read(®s->mcr), priv->read(®s->ctrl));
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return 0;
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@@ -1069,10 +1086,10 @@ static void flexcan_chip_stop(struct net
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flexcan_chip_disable(priv);
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/* Disable all interrupts */
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- flexcan_write(0, ®s->imask2);
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- flexcan_write(0, ®s->imask1);
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- flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
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- ®s->ctrl);
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+ priv->write(0, ®s->imask2);
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+ priv->write(0, ®s->imask1);
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+ priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
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+ ®s->ctrl);
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flexcan_transceiver_disable(priv);
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priv->can.state = CAN_STATE_STOPPED;
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@@ -1187,26 +1204,26 @@ static int register_flexcandev(struct ne
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err = flexcan_chip_disable(priv);
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if (err)
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goto out_disable_per;
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- reg = flexcan_read(®s->ctrl);
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+ reg = priv->read(®s->ctrl);
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reg |= FLEXCAN_CTRL_CLK_SRC;
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- flexcan_write(reg, ®s->ctrl);
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+ priv->write(reg, ®s->ctrl);
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err = flexcan_chip_enable(priv);
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if (err)
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goto out_chip_disable;
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/* set freeze, halt and activate FIFO, restrict register access */
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- reg = flexcan_read(®s->mcr);
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+ reg = priv->read(®s->mcr);
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reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
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FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
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- flexcan_write(reg, ®s->mcr);
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+ priv->write(reg, ®s->mcr);
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/* Currently we only support newer versions of this core
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* featuring a RX hardware FIFO (although this driver doesn't
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* make use of it on some cores). Older cores, found on some
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* Coldfire derivates are not tested.
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*/
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- reg = flexcan_read(®s->mcr);
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+ reg = priv->read(®s->mcr);
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if (!(reg & FLEXCAN_MCR_FEN)) {
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netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
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err = -ENODEV;
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@@ -1234,8 +1251,12 @@ static void unregister_flexcandev(struct
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static const struct of_device_id flexcan_of_match[] = {
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{ .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
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{ .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
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+ { .compatible = "fsl,imx53-flexcan", .data = &fsl_p1010_devtype_data, },
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+ { .compatible = "fsl,imx35-flexcan", .data = &fsl_p1010_devtype_data, },
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+ { .compatible = "fsl,imx25-flexcan", .data = &fsl_p1010_devtype_data, },
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{ .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
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{ .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
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+ { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, flexcan_of_match);
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@@ -1315,6 +1336,21 @@ static int flexcan_probe(struct platform
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dev->flags |= IFF_ECHO;
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priv = netdev_priv(dev);
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+
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+ if (of_property_read_bool(pdev->dev.of_node, "big-endian")) {
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+ priv->read = flexcan_read_be;
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+ priv->write = flexcan_write_be;
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+ } else {
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+ if (of_device_is_compatible(pdev->dev.of_node,
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+ "fsl,p1010-flexcan")) {
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+ priv->read = flexcan_read_be;
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+ priv->write = flexcan_write_be;
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+ } else {
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+ priv->read = flexcan_read_le;
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+ priv->write = flexcan_write_le;
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+ }
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+ }
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+
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priv->can.clock.freq = clock_freq;
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priv->can.bittiming_const = &flexcan_bittiming_const;
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priv->can.do_set_mode = flexcan_set_mode;
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