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https://github.com/openwrt/openwrt.git
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5e49c57956
1)Changes - Rebased the patches for linux-4.4.7 - Added patch to fix spi nor fifo and dma support - Added patch to configure watchdog barktime 2)Testing Tested on IPQ AP148 Board: a. NOR boot and NAND boot b. ethernet network and ath10k wifi c. ubi sysupgrade UnTested dwc3 usb has not been validated on IPQ board(AP148) 3)Known Issues: Once we flash ubi image on AP148, and if we reset the board, uboot on first boot creates PEB and LEB for dynamic sized partitions, which is incorrect and not what linux expects which causes errors when trying to mount rootfs. In order to test this, we can use the below steps: a. Flash the ubi image on board and don't reset the board b. load the kernel fit image in RAM and boot from there. Signed-off-by: Ram Chandra Jangir <rjangi@codeaurora.org>
245 lines
6.6 KiB
Diff
245 lines
6.6 KiB
Diff
From 5b40516b2f5fb9b2a7d6d3e2e924f12ec9d183a8 Mon Sep 17 00:00:00 2001
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From: Mathieu Olivari <mathieu@codeaurora.org>
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Date: Tue, 21 Apr 2015 19:01:42 -0700
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Subject: [PATCH 8/9] ARM: dts: qcom: add pcie nodes to ipq806x platforms
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qcom-pcie driver now supports version 0 of the controller. This change
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adds the corresponding entries to the IPQ806x dtsi file and
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corresponding platform (AP148).
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Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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---
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arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 30 ++++++++
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arch/arm/boot/dts/qcom-ipq8064.dtsi | 124 +++++++++++++++++++++++++++++++
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2 files changed, 154 insertions(+)
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--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -116,5 +116,15 @@
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usb30@1 {
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status = "ok";
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};
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+
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+ pcie0: pci@1b500000 {
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+ status = "ok";
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+ phy-tx0-term-offset = <7>;
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+ };
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+
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+ pcie1: pci@1b700000 {
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+ status = "ok";
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+ phy-tx0-term-offset = <7>;
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+ };
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};
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};
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--- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
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@@ -128,5 +128,17 @@
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usb30@1 {
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status = "ok";
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};
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+
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+ pcie0: pci@1b500000 {
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+ status = "ok";
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+ };
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+
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+ pcie1: pci@1b700000 {
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+ status = "ok";
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+ };
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+
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+ pcie2: pci@1b900000 {
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+ status = "ok";
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+ };
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};
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};
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -4,6 +4,9 @@
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#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
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#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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+#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Qualcomm IPQ8064";
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@@ -99,6 +102,33 @@
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 16 0x4>;
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+
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+ pcie0_pins: pcie0_pinmux {
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+ mux {
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+ pins = "gpio3";
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+ function = "pcie1_rst";
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+ drive-strength = <12>;
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+ bias-disable;
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+ };
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+ };
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+
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+ pcie1_pins: pcie1_pinmux {
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+ mux {
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+ pins = "gpio48";
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+ function = "pcie2_rst";
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+ drive-strength = <12>;
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+ bias-disable;
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+ };
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+ };
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+
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+ pcie2_pins: pcie2_pinmux {
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+ mux {
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+ pins = "gpio63";
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+ function = "pcie3_rst";
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+ drive-strength = <12>;
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+ bias-disable;
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+ };
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+ };
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};
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intc: interrupt-controller@2000000 {
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@@ -417,6 +447,144 @@
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dr_mode = "host";
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};
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};
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+
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+ pcie0: pci@1b500000 {
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+ compatible = "qcom,pcie-v0";
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+ reg = <0x1b500000 0x1000
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+ 0x1b502000 0x80
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+ 0x1b600000 0x100
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+ 0x0ff00000 0x100000>;
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+ reg-names = "dbi", "elbi", "parf", "config";
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+ device_type = "pci";
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+ linux,pci-domain = <0>;
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+ bus-range = <0x00 0xff>;
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+ num-lanes = <1>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+
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+ ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
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+ 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
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+
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+ interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
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+ interrupt-names = "msi";
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 0x7>;
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+ interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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+ <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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+ <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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+ <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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+
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+ clocks = <&gcc PCIE_A_CLK>,
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+ <&gcc PCIE_H_CLK>,
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+ <&gcc PCIE_PHY_CLK>;
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+ clock-names = "core", "iface", "phy";
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+
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+ resets = <&gcc PCIE_ACLK_RESET>,
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+ <&gcc PCIE_HCLK_RESET>,
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+ <&gcc PCIE_POR_RESET>,
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+ <&gcc PCIE_PCI_RESET>,
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+ <&gcc PCIE_PHY_RESET>;
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+ reset-names = "axi", "ahb", "por", "pci", "phy";
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+
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+ pinctrl-0 = <&pcie0_pins>;
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+ pinctrl-names = "default";
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+
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+ perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
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+
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+ status = "disabled";
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+ };
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+
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+ pcie1: pci@1b700000 {
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+ compatible = "qcom,pcie-v0";
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+ reg = <0x1b700000 0x1000
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+ 0x1b702000 0x80
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+ 0x1b800000 0x100
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+ 0x31f00000 0x100000>;
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+ reg-names = "dbi", "elbi", "parf", "config";
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+ device_type = "pci";
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+ linux,pci-domain = <1>;
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+ bus-range = <0x00 0xff>;
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+ num-lanes = <1>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+
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+ ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
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+ 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
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+
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+ interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
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+ interrupt-names = "msi";
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 0x7>;
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+ interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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+ <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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+ <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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+ <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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+
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+ clocks = <&gcc PCIE_1_A_CLK>,
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+ <&gcc PCIE_1_H_CLK>,
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+ <&gcc PCIE_1_PHY_CLK>;
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+ clock-names = "core", "iface", "phy";
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+
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+ resets = <&gcc PCIE_1_ACLK_RESET>,
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+ <&gcc PCIE_1_HCLK_RESET>,
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+ <&gcc PCIE_1_POR_RESET>,
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+ <&gcc PCIE_1_PCI_RESET>,
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+ <&gcc PCIE_1_PHY_RESET>;
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+ reset-names = "axi", "ahb", "por", "pci", "phy";
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+
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+ pinctrl-0 = <&pcie1_pins>;
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+ pinctrl-names = "default";
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+
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+ perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
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+
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+ status = "disabled";
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+ };
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+
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+ pcie2: pci@1b900000 {
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+ compatible = "qcom,pcie-v0";
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+ reg = <0x1b900000 0x1000
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+ 0x1b902000 0x80
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+ 0x1ba00000 0x100
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+ 0x35f00000 0x100000>;
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+ reg-names = "dbi", "elbi", "parf", "config";
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+ device_type = "pci";
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+ linux,pci-domain = <2>;
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+ bus-range = <0x00 0xff>;
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+ num-lanes = <1>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+
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+ ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
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+ 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
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+
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+ interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
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+ interrupt-names = "msi";
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 0x7>;
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+ interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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+ <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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+ <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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+ <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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+
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+ clocks = <&gcc PCIE_2_A_CLK>,
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+ <&gcc PCIE_2_H_CLK>,
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+ <&gcc PCIE_2_PHY_CLK>;
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+ clock-names = "core", "iface", "phy";
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+
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+ resets = <&gcc PCIE_2_ACLK_RESET>,
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+ <&gcc PCIE_2_HCLK_RESET>,
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+ <&gcc PCIE_2_POR_RESET>,
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+ <&gcc PCIE_2_PCI_RESET>,
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+ <&gcc PCIE_2_PHY_RESET>;
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+ reset-names = "axi", "ahb", "por", "pci", "phy";
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+
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+ pinctrl-0 = <&pcie2_pins>;
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+ pinctrl-names = "default";
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+
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+ perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
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+
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+ status = "disabled";
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+ };
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};
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sfpb_mutex: sfpb-mutex {
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