mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-24 15:56:49 +00:00
4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
168 lines
5.9 KiB
Diff
168 lines
5.9 KiB
Diff
From 798b9b4681be53ddbf1d8db8a88ff19aaaca500f Mon Sep 17 00:00:00 2001
|
|
From: Emil Renner Berthing <kernel@esmil.dk>
|
|
Date: Sat, 1 Apr 2023 19:19:23 +0800
|
|
Subject: [PATCH 011/122] reset: starfive: Rename "jh7100" to "jh71x0" for the
|
|
common code
|
|
|
|
For the common code will be shared with the StarFive JH7110 SoC.
|
|
|
|
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
|
|
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
|
|
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
|
|
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
|
|
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
|
|
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
|
|
---
|
|
.../reset/starfive/reset-starfive-jh7100.c | 2 +-
|
|
.../reset/starfive/reset-starfive-jh71x0.c | 50 +++++++++----------
|
|
.../reset/starfive/reset-starfive-jh71x0.h | 2 +-
|
|
3 files changed, 27 insertions(+), 27 deletions(-)
|
|
|
|
--- a/drivers/reset/starfive/reset-starfive-jh7100.c
|
|
+++ b/drivers/reset/starfive/reset-starfive-jh7100.c
|
|
@@ -51,7 +51,7 @@ static int __init jh7100_reset_probe(str
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
- return reset_starfive_jh7100_register(&pdev->dev, pdev->dev.of_node,
|
|
+ return reset_starfive_jh71x0_register(&pdev->dev, pdev->dev.of_node,
|
|
base + JH7100_RESET_ASSERT0,
|
|
base + JH7100_RESET_STATUS0,
|
|
jh7100_reset_asserted,
|
|
--- a/drivers/reset/starfive/reset-starfive-jh71x0.c
|
|
+++ b/drivers/reset/starfive/reset-starfive-jh71x0.c
|
|
@@ -1,6 +1,6 @@
|
|
// SPDX-License-Identifier: GPL-2.0-or-later
|
|
/*
|
|
- * Reset driver for the StarFive JH7100 SoC
|
|
+ * Reset driver for the StarFive JH71X0 SoCs
|
|
*
|
|
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
|
|
*/
|
|
@@ -15,7 +15,7 @@
|
|
|
|
#include "reset-starfive-jh71x0.h"
|
|
|
|
-struct jh7100_reset {
|
|
+struct jh71x0_reset {
|
|
struct reset_controller_dev rcdev;
|
|
/* protect registers against concurrent read-modify-write */
|
|
spinlock_t lock;
|
|
@@ -24,16 +24,16 @@ struct jh7100_reset {
|
|
const u64 *asserted;
|
|
};
|
|
|
|
-static inline struct jh7100_reset *
|
|
-jh7100_reset_from(struct reset_controller_dev *rcdev)
|
|
+static inline struct jh71x0_reset *
|
|
+jh71x0_reset_from(struct reset_controller_dev *rcdev)
|
|
{
|
|
- return container_of(rcdev, struct jh7100_reset, rcdev);
|
|
+ return container_of(rcdev, struct jh71x0_reset, rcdev);
|
|
}
|
|
|
|
-static int jh7100_reset_update(struct reset_controller_dev *rcdev,
|
|
+static int jh71x0_reset_update(struct reset_controller_dev *rcdev,
|
|
unsigned long id, bool assert)
|
|
{
|
|
- struct jh7100_reset *data = jh7100_reset_from(rcdev);
|
|
+ struct jh71x0_reset *data = jh71x0_reset_from(rcdev);
|
|
unsigned long offset = BIT_ULL_WORD(id);
|
|
u64 mask = BIT_ULL_MASK(id);
|
|
void __iomem *reg_assert = data->assert + offset * sizeof(u64);
|
|
@@ -62,34 +62,34 @@ static int jh7100_reset_update(struct re
|
|
return ret;
|
|
}
|
|
|
|
-static int jh7100_reset_assert(struct reset_controller_dev *rcdev,
|
|
+static int jh71x0_reset_assert(struct reset_controller_dev *rcdev,
|
|
unsigned long id)
|
|
{
|
|
- return jh7100_reset_update(rcdev, id, true);
|
|
+ return jh71x0_reset_update(rcdev, id, true);
|
|
}
|
|
|
|
-static int jh7100_reset_deassert(struct reset_controller_dev *rcdev,
|
|
+static int jh71x0_reset_deassert(struct reset_controller_dev *rcdev,
|
|
unsigned long id)
|
|
{
|
|
- return jh7100_reset_update(rcdev, id, false);
|
|
+ return jh71x0_reset_update(rcdev, id, false);
|
|
}
|
|
|
|
-static int jh7100_reset_reset(struct reset_controller_dev *rcdev,
|
|
+static int jh71x0_reset_reset(struct reset_controller_dev *rcdev,
|
|
unsigned long id)
|
|
{
|
|
int ret;
|
|
|
|
- ret = jh7100_reset_assert(rcdev, id);
|
|
+ ret = jh71x0_reset_assert(rcdev, id);
|
|
if (ret)
|
|
return ret;
|
|
|
|
- return jh7100_reset_deassert(rcdev, id);
|
|
+ return jh71x0_reset_deassert(rcdev, id);
|
|
}
|
|
|
|
-static int jh7100_reset_status(struct reset_controller_dev *rcdev,
|
|
+static int jh71x0_reset_status(struct reset_controller_dev *rcdev,
|
|
unsigned long id)
|
|
{
|
|
- struct jh7100_reset *data = jh7100_reset_from(rcdev);
|
|
+ struct jh71x0_reset *data = jh71x0_reset_from(rcdev);
|
|
unsigned long offset = BIT_ULL_WORD(id);
|
|
u64 mask = BIT_ULL_MASK(id);
|
|
void __iomem *reg_status = data->status + offset * sizeof(u64);
|
|
@@ -98,25 +98,25 @@ static int jh7100_reset_status(struct re
|
|
return !((value ^ data->asserted[offset]) & mask);
|
|
}
|
|
|
|
-static const struct reset_control_ops jh7100_reset_ops = {
|
|
- .assert = jh7100_reset_assert,
|
|
- .deassert = jh7100_reset_deassert,
|
|
- .reset = jh7100_reset_reset,
|
|
- .status = jh7100_reset_status,
|
|
+static const struct reset_control_ops jh71x0_reset_ops = {
|
|
+ .assert = jh71x0_reset_assert,
|
|
+ .deassert = jh71x0_reset_deassert,
|
|
+ .reset = jh71x0_reset_reset,
|
|
+ .status = jh71x0_reset_status,
|
|
};
|
|
|
|
-int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_node,
|
|
+int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
|
|
void __iomem *assert, void __iomem *status,
|
|
const u64 *asserted, unsigned int nr_resets,
|
|
struct module *owner)
|
|
{
|
|
- struct jh7100_reset *data;
|
|
+ struct jh71x0_reset *data;
|
|
|
|
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
|
|
if (!data)
|
|
return -ENOMEM;
|
|
|
|
- data->rcdev.ops = &jh7100_reset_ops;
|
|
+ data->rcdev.ops = &jh71x0_reset_ops;
|
|
data->rcdev.owner = owner;
|
|
data->rcdev.nr_resets = nr_resets;
|
|
data->rcdev.dev = dev;
|
|
@@ -129,4 +129,4 @@ int reset_starfive_jh7100_register(struc
|
|
|
|
return devm_reset_controller_register(dev, &data->rcdev);
|
|
}
|
|
-EXPORT_SYMBOL_GPL(reset_starfive_jh7100_register);
|
|
+EXPORT_SYMBOL_GPL(reset_starfive_jh71x0_register);
|
|
--- a/drivers/reset/starfive/reset-starfive-jh71x0.h
|
|
+++ b/drivers/reset/starfive/reset-starfive-jh71x0.h
|
|
@@ -6,7 +6,7 @@
|
|
#ifndef __RESET_STARFIVE_JH71X0_H
|
|
#define __RESET_STARFIVE_JH71X0_H
|
|
|
|
-int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_node,
|
|
+int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
|
|
void __iomem *assert, void __iomem *status,
|
|
const u64 *asserted, unsigned int nr_resets,
|
|
struct module *owner);
|