mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-21 06:33:41 +00:00
87 lines
3.2 KiB
Diff
87 lines
3.2 KiB
Diff
This fixes a boot hang observed when the bootloader
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already enabled the PCIe link for it's own use. The
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fundamental problem is that Freescale forgot to wire
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up the core reset, so software doesn't have a sane way
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to get the core into a defined state.
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According to the DW PCIe core reference manual configuration
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of the core may only happen when the LTSSM is disabled, so
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this is one of the first things we need to do. Apparently
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this isn't safe to do when the LTSSM is in any other state
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than "detect" as we observe an instant machine hang when
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trying to do so while the link is already up.
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As a workaround force LTSSM into detect state right before
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hitting the disable switch.
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Reported-by: Fabio Estevam <fabio.estevam <at> freescale.com>
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Signed-off-by: Lucas Stach <l.stach <at> pengutronix.de>
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Acked-by: Tim Harvey <tharvey <at> gateworks.com>
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--- a/drivers/pci/host/pci-imx6.c
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+++ b/drivers/pci/host/pci-imx6.c
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@@ -52,6 +52,9 @@ struct imx6_pcie {
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/* PCIe Port Logic registers (memory-mapped) */
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#define PL_OFFSET 0x700
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+#define PCIE_PL_PFLR (PL_OFFSET + 0x08)
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+#define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
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+#define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
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#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
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#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
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#define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
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@@ -217,6 +220,31 @@ static int imx6q_pcie_abort_handler(unsi
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static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
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{
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struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
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+ u32 val, gpr1, gpr12;
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+
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+ /*
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+ * If the bootloader already enabled the link we need some special
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+ * handling to get the core back into a state where it is safe to
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+ * touch it for configuration. As there is no dedicated reset signal
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+ * wired up for MX6QDL, we need to manually force LTSSM into "detect"
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+ * state before completely disabling LTSSM, which is a prerequisite
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+ * for core configuration.
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+ * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
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+ * indication that the bootloader activated the link.
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+ */
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+ regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &gpr1);
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+ regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &gpr12);
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+
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+ if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) &&
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+ (gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) {
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+ val = readl(pp->dbi_base + PCIE_PL_PFLR);
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+ val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
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+ val |= PCIE_PL_PFLR_FORCE_LINK;
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+ writel(val, pp->dbi_base + PCIE_PL_PFLR);
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+
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+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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+ IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
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+ }
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
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@@ -627,6 +655,14 @@ static int __init imx6_pcie_probe(struct
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return 0;
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}
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+static void imx6_pcie_shutdown(struct platform_device *pdev)
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+{
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+ struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
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+
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+ /* bring down link, so bootloader gets clean state in case of reboot */
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+ imx6_pcie_assert_core_reset(&imx6_pcie->pp);
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+}
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+
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static const struct of_device_id imx6_pcie_of_match[] = {
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{ .compatible = "fsl,imx6q-pcie", },
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{},
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@@ -639,6 +675,7 @@ static struct platform_driver imx6_pcie_
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.owner = THIS_MODULE,
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.of_match_table = imx6_pcie_of_match,
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},
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+ .shutdown = imx6_pcie_shutdown,
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};
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/* Freescale PCIe driver does not allow module unload */
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