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https://github.com/openwrt/openwrt.git
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79e9ce354e
Fix issue of transmitting abnormal data which leads to link problems
in 1G and 2.5G SerDes modes (SGMII, 1000Base-X, 2500Base-X) on the
MediaTek MT7988 SoC.
Link: b72d6cba92
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
499 lines
16 KiB
Diff
499 lines
16 KiB
Diff
From patchwork Thu Feb 1 21:53:06 2024
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
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X-Patchwork-Id: 13541843
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Date: Thu, 1 Feb 2024 21:53:06 +0000
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From: Daniel Golle <daniel@makrotopia.org>
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To: Bc-bocun Chen <bc-bocun.chen@mediatek.com>,
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Chunfeng Yun <chunfeng.yun@mediatek.com>,
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Vinod Koul <vkoul@kernel.org>,
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Kishon Vijay Abraham I <kishon@kernel.org>,
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Rob Herring <robh@kernel.org>,
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Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
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Conor Dooley <conor+dt@kernel.org>,
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Daniel Golle <daniel@makrotopia.org>,
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Qingfang Deng <dqfext@gmail.com>,
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SkyLake Huang <SkyLake.Huang@mediatek.com>,
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Matthias Brugger <matthias.bgg@gmail.com>,
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AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
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Philipp Zabel <p.zabel@pengutronix.de>,
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linux-arm-kernel@lists.infradead.org,
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linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org,
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devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
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netdev@vger.kernel.org
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Subject: [PATCH 2/2] phy: add driver for MediaTek XFI T-PHY
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Message-ID:
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<dd6b40ea1f7f8459a9a2cfe7fa60c1108332ade6.1706823233.git.daniel@makrotopia.org>
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References:
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<702afb0c1246d95c90b22e57105304028bdd3083.1706823233.git.daniel@makrotopia.org>
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MIME-Version: 1.0
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Content-Disposition: inline
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In-Reply-To:
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<702afb0c1246d95c90b22e57105304028bdd3083.1706823233.git.daniel@makrotopia.org>
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List-Id: Linux Phy Mailing list <linux-phy.lists.infradead.org>
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Add driver for MediaTek's XFI T-PHY, 10 Gigabit/s Ethernet SerDes PHY
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which can be found in the MT7988 SoC.
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The PHY can operates only in PHY_MODE_ETHERNET, the submode is one of
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PHY_INTERFACE_MODE_* corresponding to the supported modes:
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* USXGMII \
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* 10GBase-R }- USXGMII PCS - XGDM \
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* 5GBase-R / \
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}- Ethernet MAC
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* 2500Base-X \ /
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* 1000Base-X }- LynxI PCS - GDM /
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* Cisco SGMII (MAC side) /
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In order to work-around a performance issue present on the first of
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two XFI T-PHYs present in MT7988, special tuning is applied which can be
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selected by adding the 'mediatek,usxgmii-performance-errata' property to
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the device tree node.
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There is no documentation for most registers used for the
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analog/tuning part, however, most of the registers have been partially
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reverse-engineered from MediaTek's SDK implementation (an opaque
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sequence of 32-bit register writes) and descriptions for all relevant
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digital registers and bits such as resets and muxes have been supplied
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by MediaTek.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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MAINTAINERS | 1 +
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drivers/phy/mediatek/Kconfig | 12 +
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drivers/phy/mediatek/Makefile | 1 +
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drivers/phy/mediatek/phy-mtk-xfi-tphy.c | 392 ++++++++++++++++++++++++
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4 files changed, 406 insertions(+)
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create mode 100644 drivers/phy/mediatek/phy-mtk-xfi-tphy.c
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--- a/drivers/phy/mediatek/Kconfig
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+++ b/drivers/phy/mediatek/Kconfig
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@@ -13,6 +13,18 @@ config PHY_MTK_PCIE
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callback for PCIe GEN3 port, it supports software efuse
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initialization.
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+config PHY_MTK_XFI_TPHY
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+ tristate "MediaTek XFI T-PHY Driver"
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+ depends on ARCH_MEDIATEK || COMPILE_TEST
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+ depends on OF && OF_ADDRESS
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+ depends on HAS_IOMEM
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+ select GENERIC_PHY
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+ help
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+ Say 'Y' here to add support for MediaTek XFI T-PHY driver.
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+ The driver provides access to the Ethernet SerDes T-PHY supporting
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+ 1GE and 2.5GE modes via the LynxI PCS, and 5GE and 10GE modes
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+ via the USXGMII PCS found in MediaTek SoCs with 10G Ethernet.
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+
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config PHY_MTK_TPHY
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tristate "MediaTek T-PHY Driver"
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depends on ARCH_MEDIATEK || COMPILE_TEST
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--- a/drivers/phy/mediatek/Makefile
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+++ b/drivers/phy/mediatek/Makefile
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@@ -8,6 +8,7 @@ obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-p
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obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
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obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
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obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
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+obj-$(CONFIG_PHY_MTK_XFI_TPHY) += phy-mtk-xfi-tphy.o
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phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
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phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
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--- /dev/null
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+++ b/drivers/phy/mediatek/phy-mtk-xfi-tphy.c
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@@ -0,0 +1,393 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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+/* MediaTek 10GE SerDes PHY driver
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+ *
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+ * Copyright (c) 2024 Daniel Golle <daniel@makrotopia.org>
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+ * Bc-bocun Chen <bc-bocun.chen@mediatek.com>
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+ * based on mtk_usxgmii.c found in MediaTek's SDK released under GPL-2.0
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+ * Copyright (c) 2022 MediaTek Inc.
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+ * Author: Henry Yen <henry.yen@mediatek.com>
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/device.h>
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+#include <linux/platform_device.h>
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+#include <linux/of.h>
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+#include <linux/io.h>
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+#include <linux/clk.h>
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+#include <linux/reset.h>
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+#include <linux/phy.h>
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+#include <linux/phy/phy.h>
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+
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+#define MTK_XFI_TPHY_NUM_CLOCKS 2
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+
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+#define REG_DIG_GLB_70 0x0070
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+#define XTP_PCS_RX_EQ_IN_PROGRESS(x) FIELD_PREP(GENMASK(25, 24), (x))
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+#define XTP_PCS_MODE_MASK GENMASK(17, 16)
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+#define XTP_PCS_MODE(x) FIELD_PREP(GENMASK(17, 16), (x))
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+#define XTP_PCS_RST_B BIT(15)
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+#define XTP_FRC_PCS_RST_B BIT(14)
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+#define XTP_PCS_PWD_SYNC_MASK GENMASK(13, 12)
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+#define XTP_PCS_PWD_SYNC(x) FIELD_PREP(XTP_PCS_PWD_SYNC_MASK, (x))
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+#define XTP_PCS_PWD_ASYNC_MASK GENMASK(11, 10)
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+#define XTP_PCS_PWD_ASYNC(x) FIELD_PREP(XTP_PCS_PWD_ASYNC_MASK, (x))
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+#define XTP_FRC_PCS_PWD_ASYNC BIT(8)
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+#define XTP_PCS_UPDT BIT(4)
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+#define XTP_PCS_IN_FR_RG BIT(0)
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+
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+#define REG_DIG_GLB_F4 0x00f4
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+#define XFI_DPHY_PCS_SEL BIT(0)
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+#define XFI_DPHY_PCS_SEL_SGMII FIELD_PREP(XFI_DPHY_PCS_SEL, 1)
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+#define XFI_DPHY_PCS_SEL_USXGMII FIELD_PREP(XFI_DPHY_PCS_SEL, 0)
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+#define XFI_DPHY_AD_SGDT_FRC_EN BIT(5)
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+
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+#define REG_DIG_LN_TRX_40 0x3040
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+#define XTP_LN_FRC_TX_DATA_EN BIT(29)
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+#define XTP_LN_TX_DATA_EN BIT(28)
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+
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+#define REG_DIG_LN_TRX_B0 0x30b0
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+#define XTP_LN_FRC_TX_MACCK_EN BIT(5)
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+#define XTP_LN_TX_MACCK_EN BIT(4)
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+
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+#define REG_ANA_GLB_D0 0x90d0
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+#define XTP_GLB_USXGMII_SEL_MASK GENMASK(3, 1)
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+#define XTP_GLB_USXGMII_SEL(x) FIELD_PREP(GENMASK(3, 1), (x))
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+#define XTP_GLB_USXGMII_EN BIT(0)
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+
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+struct mtk_xfi_tphy {
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+ void __iomem *base;
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+ struct device *dev;
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+ struct reset_control *reset;
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+ struct clk_bulk_data clocks[MTK_XFI_TPHY_NUM_CLOCKS];
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+ bool da_war;
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+};
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+
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+static void mtk_xfi_tphy_write(struct mtk_xfi_tphy *xfi_tphy, u16 reg,
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+ u32 value)
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+{
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+ iowrite32(value, xfi_tphy->base + reg);
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+}
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+
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+static void mtk_xfi_tphy_rmw(struct mtk_xfi_tphy *xfi_tphy, u16 reg,
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+ u32 clr, u32 set)
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+{
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+ u32 val;
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+
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+ val = ioread32(xfi_tphy->base + reg);
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+ val &= ~clr;
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+ val |= set;
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+ iowrite32(val, xfi_tphy->base + reg);
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+}
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+
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+static void mtk_xfi_tphy_set(struct mtk_xfi_tphy *xfi_tphy, u16 reg,
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+ u32 set)
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+{
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+ mtk_xfi_tphy_rmw(xfi_tphy, reg, 0, set);
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+}
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+
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+static void mtk_xfi_tphy_clear(struct mtk_xfi_tphy *xfi_tphy, u16 reg,
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+ u32 clr)
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+{
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+ mtk_xfi_tphy_rmw(xfi_tphy, reg, clr, 0);
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+}
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+
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+static void mtk_xfi_tphy_setup(struct mtk_xfi_tphy *xfi_tphy,
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+ phy_interface_t interface)
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+{
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+ bool is_2p5g = (interface == PHY_INTERFACE_MODE_2500BASEX);
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+ bool is_1g = (interface == PHY_INTERFACE_MODE_1000BASEX ||
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+ interface == PHY_INTERFACE_MODE_SGMII);
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+ bool is_10g = (interface == PHY_INTERFACE_MODE_10GBASER ||
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+ interface == PHY_INTERFACE_MODE_USXGMII);
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+ bool is_5g = (interface == PHY_INTERFACE_MODE_5GBASER);
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+ bool is_xgmii = (is_10g || is_5g);
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+
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+ dev_dbg(xfi_tphy->dev, "setting up for mode %s\n", phy_modes(interface));
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+
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+ /* Setup PLL setting */
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+ mtk_xfi_tphy_rmw(xfi_tphy, 0x9024, 0x100000, is_10g ? 0x0 : 0x100000);
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+ mtk_xfi_tphy_rmw(xfi_tphy, 0x2020, 0x202000, is_5g ? 0x202000 : 0x0);
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+ mtk_xfi_tphy_rmw(xfi_tphy, 0x2030, 0x500, is_1g ? 0x0 : 0x500);
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+ mtk_xfi_tphy_rmw(xfi_tphy, 0x2034, 0xa00, is_1g ? 0x0 : 0xa00);
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+ mtk_xfi_tphy_rmw(xfi_tphy, 0x2040, 0x340000, is_1g ? 0x200000 :
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+ 0x140000);
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+
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+ /* Setup RXFE BW setting */
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+ mtk_xfi_tphy_rmw(xfi_tphy, 0x50f0, 0xc10, is_1g ? 0x410 :
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+ is_5g ? 0x800 : 0x400);
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+ mtk_xfi_tphy_rmw(xfi_tphy, 0x50e0, 0x4000, is_5g ? 0x0 : 0x4000);
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+
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+ /* Setup RX CDR setting */
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+ mtk_xfi_tphy_rmw(xfi_tphy, 0x506c, 0x30000, is_5g ? 0x0 : 0x30000);
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+ mtk_xfi_tphy_rmw(xfi_tphy, 0x5070, 0x670000, is_5g ? 0x620000 : 0x50000);
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+ mtk_xfi_tphy_rmw(xfi_tphy, 0x5074, 0x180000, is_5g ? 0x180000 : 0x0);
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+ mtk_xfi_tphy_rmw(xfi_tphy, 0x5078, 0xf000400, is_5g ? 0x8000000 :
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+ 0x7000400);
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+ mtk_xfi_tphy_rmw(xfi_tphy, 0x507c, 0x5000500, is_5g ? 0x4000400 :
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+ 0x1000100);
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+ mtk_xfi_tphy_rmw(xfi_tphy, 0x5080, 0x1410, is_1g ? 0x400 :
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+ is_5g ? 0x1010 : 0x0);
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+ mtk_xfi_tphy_rmw(xfi_tphy, 0x5084, 0x30300, is_1g ? 0x30300 :
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+ is_5g ? 0x30100 :
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+ 0x100);
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+ mtk_xfi_tphy_rmw(xfi_tphy, 0x5088, 0x60200, is_1g ? 0x20200 :
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+ is_5g ? 0x40000 :
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+ 0x20000);
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+
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+ /* Setting RXFE adaptation range setting */
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+ mtk_xfi_tphy_rmw(xfi_tphy, 0x50e4, 0xc0000, is_5g ? 0x0 : 0xc0000);
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+ mtk_xfi_tphy_rmw(xfi_tphy, 0x50e8, 0x40000, is_5g ? 0x0 : 0x40000);
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+ mtk_xfi_tphy_rmw(xfi_tphy, 0x50ec, 0xa00, is_1g ? 0x200 : 0x800);
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+ mtk_xfi_tphy_rmw(xfi_tphy, 0x50a8, 0xee0000, is_5g ? 0x800000 :
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+ 0x6e0000);
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+ mtk_xfi_tphy_rmw(xfi_tphy, 0x6004, 0x190000, is_5g ? 0x0 : 0x190000);
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+ if (is_10g)
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+ mtk_xfi_tphy_write(xfi_tphy, 0x00f8, 0x01423342);
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+ else if (is_5g)
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+ mtk_xfi_tphy_write(xfi_tphy, 0x00f8, 0x00a132a1);
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+ else if (is_2p5g)
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+ mtk_xfi_tphy_write(xfi_tphy, 0x00f8, 0x009c329c);
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+ else
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+ mtk_xfi_tphy_write(xfi_tphy, 0x00f8, 0x00fa32fa);
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+
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+ /* Force SGDT_OUT off and select PCS */
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+ mtk_xfi_tphy_rmw(xfi_tphy, REG_DIG_GLB_F4,
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+ XFI_DPHY_AD_SGDT_FRC_EN | XFI_DPHY_PCS_SEL,
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+ XFI_DPHY_AD_SGDT_FRC_EN |
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+ (is_xgmii ? XFI_DPHY_PCS_SEL_USXGMII :
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+ XFI_DPHY_PCS_SEL_SGMII));
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+
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+
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+ /* Force GLB_CKDET_OUT */
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+ mtk_xfi_tphy_set(xfi_tphy, 0x0030, 0xc00);
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+
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+ /* Force AEQ on */
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+ mtk_xfi_tphy_write(xfi_tphy, REG_DIG_GLB_70,
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+ XTP_PCS_RX_EQ_IN_PROGRESS(2) |
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+ XTP_PCS_PWD_SYNC(2) |
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+ XTP_PCS_PWD_ASYNC(2));
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+
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+ usleep_range(1, 5);
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+ writel(XTP_LN_FRC_TX_DATA_EN, xfi_tphy->base + REG_DIG_LN_TRX_40);
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+
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+ /* Setup TX DA default value */
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+ mtk_xfi_tphy_rmw(xfi_tphy, 0x30b0, 0x30, 0x20);
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+ mtk_xfi_tphy_write(xfi_tphy, 0x3028, 0x00008a01);
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+ mtk_xfi_tphy_write(xfi_tphy, 0x302c, 0x0000a884);
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+ mtk_xfi_tphy_write(xfi_tphy, 0x3024, 0x00083002);
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+
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+ /* Setup RG default value */
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+ if (is_xgmii) {
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+ mtk_xfi_tphy_write(xfi_tphy, 0x3010, 0x00022220);
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+ mtk_xfi_tphy_write(xfi_tphy, 0x5064, 0x0f020a01);
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+ mtk_xfi_tphy_write(xfi_tphy, 0x50b4, 0x06100600);
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+ if (interface == PHY_INTERFACE_MODE_USXGMII)
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+ mtk_xfi_tphy_write(xfi_tphy, 0x3048, 0x40704000);
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+ else
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+ mtk_xfi_tphy_write(xfi_tphy, 0x3048, 0x47684100);
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+ } else {
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+ mtk_xfi_tphy_write(xfi_tphy, 0x3010, 0x00011110);
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+ mtk_xfi_tphy_write(xfi_tphy, 0x3048, 0x40704000);
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+ }
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+
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+ if (is_1g)
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+ mtk_xfi_tphy_write(xfi_tphy, 0x3064, 0x0000c000);
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+
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+ /* Setup RX EQ initial value */
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+ mtk_xfi_tphy_rmw(xfi_tphy, 0x3050, 0xa8000000,
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+ (interface != PHY_INTERFACE_MODE_10GBASER) ?
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+ 0xa8000000 : 0x0);
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+ mtk_xfi_tphy_rmw(xfi_tphy, 0x3054, 0xaa,
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+ (interface != PHY_INTERFACE_MODE_10GBASER) ?
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+ 0xaa : 0x0);
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+
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+ if (is_xgmii)
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+ mtk_xfi_tphy_write(xfi_tphy, 0x306c, 0x00000f00);
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+ else if (is_2p5g)
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+ mtk_xfi_tphy_write(xfi_tphy, 0x306c, 0x22000f00);
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+ else
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+ mtk_xfi_tphy_write(xfi_tphy, 0x306c, 0x20200f00);
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+
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+ if (interface == PHY_INTERFACE_MODE_10GBASER && xfi_tphy->da_war)
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+ mtk_xfi_tphy_rmw(xfi_tphy, 0xa008, 0x10000, 0x10000);
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+
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+ mtk_xfi_tphy_rmw(xfi_tphy, 0xa060, 0x50000, is_xgmii ? 0x40000 :
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+ 0x50000);
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+
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+ /* Setup PHYA speed */
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+ mtk_xfi_tphy_rmw(xfi_tphy, REG_ANA_GLB_D0,
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+ XTP_GLB_USXGMII_SEL_MASK | XTP_GLB_USXGMII_EN,
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+ is_10g ? XTP_GLB_USXGMII_SEL(0) :
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+ is_5g ? XTP_GLB_USXGMII_SEL(1) :
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+ is_2p5g ? XTP_GLB_USXGMII_SEL(2) :
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+ XTP_GLB_USXGMII_SEL(3));
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+ mtk_xfi_tphy_set(xfi_tphy, REG_ANA_GLB_D0, XTP_GLB_USXGMII_EN);
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+
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+ /* Release reset */
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+ mtk_xfi_tphy_set(xfi_tphy, REG_DIG_GLB_70,
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+ XTP_PCS_RST_B | XTP_FRC_PCS_RST_B);
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+ usleep_range(150, 500);
|
|
+
|
|
+ /* Switch to P0 */
|
|
+ mtk_xfi_tphy_rmw(xfi_tphy, REG_DIG_GLB_70,
|
|
+ XTP_PCS_PWD_SYNC_MASK |
|
|
+ XTP_PCS_PWD_ASYNC_MASK,
|
|
+ XTP_FRC_PCS_PWD_ASYNC |
|
|
+ XTP_PCS_UPDT | XTP_PCS_IN_FR_RG);
|
|
+ usleep_range(1, 5);
|
|
+
|
|
+ mtk_xfi_tphy_clear(xfi_tphy, REG_DIG_GLB_70, XTP_PCS_UPDT);
|
|
+ usleep_range(15, 50);
|
|
+
|
|
+ if (is_xgmii) {
|
|
+ /* Switch to Gen3 */
|
|
+ mtk_xfi_tphy_rmw(xfi_tphy, REG_DIG_GLB_70,
|
|
+ XTP_PCS_MODE_MASK | XTP_PCS_UPDT,
|
|
+ XTP_PCS_MODE(2) | XTP_PCS_UPDT);
|
|
+ } else {
|
|
+ /* Switch to Gen2 */
|
|
+ mtk_xfi_tphy_rmw(xfi_tphy, REG_DIG_GLB_70,
|
|
+ XTP_PCS_MODE_MASK | XTP_PCS_UPDT,
|
|
+ XTP_PCS_MODE(1) | XTP_PCS_UPDT);
|
|
+ }
|
|
+ usleep_range(1, 5);
|
|
+
|
|
+ mtk_xfi_tphy_clear(xfi_tphy, REG_DIG_GLB_70, XTP_PCS_UPDT);
|
|
+
|
|
+ usleep_range(100, 500);
|
|
+
|
|
+ /* Enable MAC CK */
|
|
+ mtk_xfi_tphy_set(xfi_tphy, REG_DIG_LN_TRX_B0, XTP_LN_TX_MACCK_EN);
|
|
+ mtk_xfi_tphy_clear(xfi_tphy, REG_DIG_GLB_F4, XFI_DPHY_AD_SGDT_FRC_EN);
|
|
+
|
|
+ /* Enable TX data */
|
|
+ mtk_xfi_tphy_set(xfi_tphy, REG_DIG_LN_TRX_40,
|
|
+ XTP_LN_FRC_TX_DATA_EN | XTP_LN_TX_DATA_EN);
|
|
+ usleep_range(400, 1000);
|
|
+}
|
|
+
|
|
+static int mtk_xfi_tphy_set_mode(struct phy *phy, enum phy_mode mode, int
|
|
+ submode)
|
|
+{
|
|
+ struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
|
|
+
|
|
+ if (mode != PHY_MODE_ETHERNET)
|
|
+ return -EINVAL;
|
|
+
|
|
+ switch (submode) {
|
|
+ case PHY_INTERFACE_MODE_1000BASEX:
|
|
+ case PHY_INTERFACE_MODE_2500BASEX:
|
|
+ case PHY_INTERFACE_MODE_SGMII:
|
|
+ case PHY_INTERFACE_MODE_5GBASER:
|
|
+ case PHY_INTERFACE_MODE_10GBASER:
|
|
+ case PHY_INTERFACE_MODE_USXGMII:
|
|
+ mtk_xfi_tphy_setup(xfi_tphy, submode);
|
|
+ return 0;
|
|
+ default:
|
|
+ return -EINVAL;
|
|
+ }
|
|
+}
|
|
+
|
|
+static int mtk_xfi_tphy_reset(struct phy *phy)
|
|
+{
|
|
+ struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
|
|
+
|
|
+ reset_control_assert(xfi_tphy->reset);
|
|
+ usleep_range(100, 500);
|
|
+ reset_control_deassert(xfi_tphy->reset);
|
|
+ usleep_range(1, 10);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int mtk_xfi_tphy_power_on(struct phy *phy)
|
|
+{
|
|
+ struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
|
|
+
|
|
+ return clk_bulk_prepare_enable(MTK_XFI_TPHY_NUM_CLOCKS, xfi_tphy->clocks);
|
|
+}
|
|
+
|
|
+static int mtk_xfi_tphy_power_off(struct phy *phy)
|
|
+{
|
|
+ struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
|
|
+
|
|
+ clk_bulk_disable_unprepare(MTK_XFI_TPHY_NUM_CLOCKS, xfi_tphy->clocks);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static const struct phy_ops mtk_xfi_tphy_ops = {
|
|
+ .power_on = mtk_xfi_tphy_power_on,
|
|
+ .power_off = mtk_xfi_tphy_power_off,
|
|
+ .set_mode = mtk_xfi_tphy_set_mode,
|
|
+ .reset = mtk_xfi_tphy_reset,
|
|
+ .owner = THIS_MODULE,
|
|
+};
|
|
+
|
|
+static int mtk_xfi_tphy_probe(struct platform_device *pdev)
|
|
+{
|
|
+ struct device_node *np = pdev->dev.of_node;
|
|
+ struct phy_provider *phy_provider;
|
|
+ struct mtk_xfi_tphy *xfi_tphy;
|
|
+ struct phy *phy;
|
|
+
|
|
+ if (!np)
|
|
+ return -ENODEV;
|
|
+
|
|
+ xfi_tphy = devm_kzalloc(&pdev->dev, sizeof(*xfi_tphy), GFP_KERNEL);
|
|
+ if (!xfi_tphy)
|
|
+ return -ENOMEM;
|
|
+
|
|
+ xfi_tphy->base = devm_of_iomap(&pdev->dev, np, 0, NULL);
|
|
+ if (!xfi_tphy->base)
|
|
+ return -EIO;
|
|
+
|
|
+ xfi_tphy->dev = &pdev->dev;
|
|
+
|
|
+ xfi_tphy->clocks[0].id = "topxtal";
|
|
+ xfi_tphy->clocks[0].clk = devm_clk_get(&pdev->dev, xfi_tphy->clocks[0].id);
|
|
+ if (IS_ERR(xfi_tphy->clocks[0].clk))
|
|
+ return PTR_ERR(xfi_tphy->clocks[0].clk);
|
|
+
|
|
+ xfi_tphy->clocks[1].id = "xfipll";
|
|
+ xfi_tphy->clocks[1].clk = devm_clk_get(&pdev->dev, xfi_tphy->clocks[1].id);
|
|
+ if (IS_ERR(xfi_tphy->clocks[1].clk))
|
|
+ return PTR_ERR(xfi_tphy->clocks[1].clk);
|
|
+
|
|
+ xfi_tphy->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
|
|
+ if (IS_ERR(xfi_tphy->reset))
|
|
+ return PTR_ERR(xfi_tphy->reset);
|
|
+
|
|
+ xfi_tphy->da_war = of_property_read_bool(np,
|
|
+ "mediatek,usxgmii-performance-errata");
|
|
+
|
|
+ phy = devm_phy_create(&pdev->dev, NULL, &mtk_xfi_tphy_ops);
|
|
+ if (IS_ERR(phy))
|
|
+ return PTR_ERR(phy);
|
|
+
|
|
+ phy_set_drvdata(phy, xfi_tphy);
|
|
+
|
|
+ phy_provider = devm_of_phy_provider_register(&pdev->dev,
|
|
+ of_phy_simple_xlate);
|
|
+
|
|
+ return PTR_ERR_OR_ZERO(phy_provider);
|
|
+}
|
|
+
|
|
+static const struct of_device_id mtk_xfi_tphy_match[] = {
|
|
+ { .compatible = "mediatek,mt7988-xfi-tphy", },
|
|
+ { }
|
|
+};
|
|
+MODULE_DEVICE_TABLE(of, mtk_xfi_tphy_match);
|
|
+
|
|
+static struct platform_driver mtk_xfi_tphy_driver = {
|
|
+ .probe = mtk_xfi_tphy_probe,
|
|
+ .driver = {
|
|
+ .name = "mtk-xfi-tphy",
|
|
+ .of_match_table = mtk_xfi_tphy_match,
|
|
+ },
|
|
+};
|
|
+module_platform_driver(mtk_xfi_tphy_driver);
|
|
+
|
|
+MODULE_DESCRIPTION("MediaTek XFI T-PHY driver");
|
|
+MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
|
|
+MODULE_AUTHOR("Bc-bocun Chen <bc-bocun.chen@mediatek.com>");
|
|
+MODULE_LICENSE("GPL");
|