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62b7f5931c
bcm2708: boot tested on RPi B+ v1.2
bcm2709: boot tested on RPi 3B v1.2 and RPi 4B v1.1 4G
bcm2710: boot tested on RPi 3B v1.2
bcm2711: boot tested on RPi 4B v1.1 4G
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
(cherry-picked from commit f07e572f64)
61 lines
2.0 KiB
Diff
61 lines
2.0 KiB
Diff
From 965cce6b1c6acc25d7cfd29ccf95c8ebbf1d7f57 Mon Sep 17 00:00:00 2001
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From: Phil Elwell <phil@raspberrypi.com>
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Date: Wed, 29 Jul 2020 13:47:55 +0100
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Subject: [PATCH] ARM: proc-v7: Force misalignment of early stmia
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In an attempt to prevent the problem of CPUn not starting, explicitly
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misalign the scratch space used to save registers acros the cache
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invalidation.
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Notes:
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At this stage in the boot process the core is running with its cache
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disabled. Before enabling the cache its contents must be explicitly
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invalidated, a process that requires quite a few registers that the
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caller must preserve. Evidence suggests that something is writing a
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block of zeroes over that space at a time when all other cores should
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be idle, possibly some kind of write-combiner, and the misalignment is
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designed to disrupt any write-coalescing.
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In truth, I don't understand why this patch works, and when the failure
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is so random it is hard to be certain that this isn't just rolling the
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dice again. One interesting test would be to change the "addeq r12, #4"s
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to "addeq r12, #0"s determine see if the offset itself is significant or
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just the additional code.
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See: https://github.com/Hexxeh/rpi-firmware/issues/232
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Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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---
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arch/arm/mm/proc-v7.S | 6 +++++-
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1 file changed, 5 insertions(+), 1 deletion(-)
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--- a/arch/arm/mm/proc-v7.S
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+++ b/arch/arm/mm/proc-v7.S
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@@ -287,6 +287,8 @@ __v7_ca17mp_setup:
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mov r10, #0
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1: adr r0, __v7_setup_stack_ptr
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ldr r12, [r0]
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+ tst r12, #0x1f
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+ addeq r12, r12, #4
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add r12, r12, r0 @ the local stack
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stmia r12, {r1-r6, lr} @ v7_invalidate_l1 touches r0-r6
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bl v7_invalidate_l1
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@@ -474,6 +476,8 @@ __v7_setup:
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adr r0, __v7_setup_stack_ptr
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ldr r12, [r0]
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add r12, r12, r0 @ the local stack
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+ tst r12, #0x1f
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+ addeq r12, r12, #4
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stmia r12, {r1-r6, lr} @ v7_invalidate_l1 touches r0-r6
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bl v7_invalidate_l1
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ldmia r12, {r1-r6, lr}
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@@ -557,7 +561,7 @@ ENDPROC(__v7_setup)
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.bss
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.align 2
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__v7_setup_stack:
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- .space 4 * 7 @ 7 registers
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+ .space 4 * 8 @ 7 registers + 1 spare
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__INITDATA
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