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62b7f5931c
bcm2708: boot tested on RPi B+ v1.2
bcm2709: boot tested on RPi 3B v1.2 and RPi 4B v1.1 4G
bcm2710: boot tested on RPi 3B v1.2
bcm2711: boot tested on RPi 4B v1.1 4G
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
(cherry-picked from commit f07e572f64)
182 lines
4.9 KiB
Diff
182 lines
4.9 KiB
Diff
From be2df6c864ba668364011301530372f5b8798593 Mon Sep 17 00:00:00 2001
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From: Markus Proeller <markus.proeller@pieye.org>
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Date: Tue, 16 Jun 2020 13:33:56 +0200
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Subject: [PATCH] media: irs1125: Keep HW in sync after imager reset
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When closing the video device, the irs1125 is put in power down state.
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To keep V4L2 ctrls and the HW in sync, v4l2_ctrl_handler_setup is
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called after power up.
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The compound ctrl IRS1125_CID_MOD_PLL however has a default value
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of all zeros, which puts the imager into a non responding state.
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Thus, this ctrl is not written by the driver into HW after power up.
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The userspace has to take care to write senseful data.
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Signed-off-by: Markus Proeller <markus.proeller@pieye.org>
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---
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drivers/media/i2c/irs1125.c | 121 +++++++++++++++++-------------------
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1 file changed, 58 insertions(+), 63 deletions(-)
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--- a/drivers/media/i2c/irs1125.c
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+++ b/drivers/media/i2c/irs1125.c
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@@ -82,6 +82,7 @@ struct irs1125 {
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struct v4l2_ctrl *ctrl_numseq;
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int power_count;
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+ bool mod_pll_init;
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};
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static inline struct irs1125 *to_state(struct v4l2_subdev *sd)
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@@ -276,8 +277,7 @@ static struct regval_list irs1125_seq_cf
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{0xC039, 0x0000},
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{0xC401, 0x0002},
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- {0xFFFF, 1},
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- {0xA87C, 0x0001}
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+ {0xFFFF, 1}
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};
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static int irs1125_write(struct v4l2_subdev *sd, u16 reg, u16 val)
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@@ -471,7 +471,11 @@ static int __sensor_init(struct v4l2_sub
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return ret;
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}
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- return 0;
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+ irs1125->mod_pll_init = true;
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+ v4l2_ctrl_handler_setup(&irs1125->ctrl_handler);
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+ irs1125->mod_pll_init = false;
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+
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+ return irs1125_write(sd, 0xA87C, 0x0001);
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}
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static int irs1125_sensor_power(struct v4l2_subdev *sd, int on)
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@@ -607,8 +611,6 @@ static int irs1125_s_ctrl(struct v4l2_ct
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struct irs1125 *dev = container_of(ctrl->handler,
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struct irs1125, ctrl_handler);
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struct i2c_client *client = v4l2_get_subdevdata(&dev->sd);
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- struct irs1125_mod_pll *mod_cur, *mod_new;
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- u16 addr, val;
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int err = 0, i;
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switch (ctrl->id) {
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@@ -660,68 +662,61 @@ static int irs1125_s_ctrl(struct v4l2_ct
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ctrl->val);
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break;
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}
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- case IRS1125_CID_MOD_PLL:
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+ case IRS1125_CID_MOD_PLL: {
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+ struct irs1125_mod_pll *mod_new;
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+
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+ if (dev->mod_pll_init)
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+ break;
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+
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mod_new = (struct irs1125_mod_pll *)ctrl->p_new.p;
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- mod_cur = (struct irs1125_mod_pll *)ctrl->p_cur.p;
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for (i = 0; i < IRS1125_NUM_MOD_PLLS; i++) {
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- if (mod_cur[i].pllcfg1 != mod_new[i].pllcfg1) {
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- addr = 0xC3A0 + i * 3;
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- val = mod_new[i].pllcfg1;
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- err = irs1125_write(&dev->sd, addr, val);
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- if (err < 0)
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- break;
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- }
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- if (mod_cur[i].pllcfg2 != mod_new[i].pllcfg2) {
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- addr = 0xC3A1 + i * 3;
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- val = mod_new[i].pllcfg2;
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- err = irs1125_write(&dev->sd, addr, val);
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- if (err < 0)
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- break;
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- }
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- if (mod_cur[i].pllcfg3 != mod_new[i].pllcfg3) {
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- addr = 0xC3A2 + i * 3;
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- val = mod_new[i].pllcfg3;
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- err = irs1125_write(&dev->sd, addr, val);
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- if (err < 0)
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- break;
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- }
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- if (mod_cur[i].pllcfg4 != mod_new[i].pllcfg4) {
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- addr = 0xC24C + i * 5;
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- val = mod_new[i].pllcfg4;
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- err = irs1125_write(&dev->sd, addr, val);
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- if (err < 0)
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- break;
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- }
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- if (mod_cur[i].pllcfg5 != mod_new[i].pllcfg5) {
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- addr = 0xC24D + i * 5;
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- val = mod_new[i].pllcfg5;
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- err = irs1125_write(&dev->sd, addr, val);
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- if (err < 0)
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- break;
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- }
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- if (mod_cur[i].pllcfg6 != mod_new[i].pllcfg6) {
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- addr = 0xC24E + i * 5;
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- val = mod_new[i].pllcfg6;
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- err = irs1125_write(&dev->sd, addr, val);
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- if (err < 0)
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- break;
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- }
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- if (mod_cur[i].pllcfg7 != mod_new[i].pllcfg7) {
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- addr = 0xC24F + i * 5;
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- val = mod_new[i].pllcfg7;
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- err = irs1125_write(&dev->sd, addr, val);
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- if (err < 0)
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- break;
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- }
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- if (mod_cur[i].pllcfg8 != mod_new[i].pllcfg8) {
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- addr = 0xC250 + i * 5;
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- val = mod_new[i].pllcfg8;
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- err = irs1125_write(&dev->sd, addr, val);
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- if (err < 0)
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- break;
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- }
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+ unsigned int pll_offset, ssc_offset;
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+
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+ pll_offset = i * 3;
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+ ssc_offset = i * 5;
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+
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+ err = irs1125_write(&dev->sd, 0xC3A0 + pll_offset,
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+ mod_new[i].pllcfg1);
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+ if (err < 0)
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+ break;
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+
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+ err = irs1125_write(&dev->sd, 0xC3A1 + pll_offset,
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+ mod_new[i].pllcfg2);
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+ if (err < 0)
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+ break;
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+
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+ err = irs1125_write(&dev->sd, 0xC3A2 + pll_offset,
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+ mod_new[i].pllcfg3);
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+ if (err < 0)
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+ break;
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+
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+ err = irs1125_write(&dev->sd, 0xC24C + ssc_offset,
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+ mod_new[i].pllcfg4);
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+ if (err < 0)
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+ break;
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+
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+ err = irs1125_write(&dev->sd, 0xC24D + ssc_offset,
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+ mod_new[i].pllcfg5);
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+ if (err < 0)
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+ break;
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+
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+ err = irs1125_write(&dev->sd, 0xC24E + ssc_offset,
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+ mod_new[i].pllcfg6);
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+ if (err < 0)
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+ break;
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+
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+ err = irs1125_write(&dev->sd, 0xC24F + ssc_offset,
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+ mod_new[i].pllcfg7);
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+ if (err < 0)
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+ break;
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+
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+ err = irs1125_write(&dev->sd, 0xC250 + ssc_offset,
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+ mod_new[i].pllcfg8);
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+ if (err < 0)
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+ break;
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}
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break;
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+ }
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case IRS1125_CID_SEQ_CONFIG: {
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struct irs1125_seq_cfg *cfg_new;
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