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62b7f5931c
bcm2708: boot tested on RPi B+ v1.2
bcm2709: boot tested on RPi 3B v1.2 and RPi 4B v1.1 4G
bcm2710: boot tested on RPi 3B v1.2
bcm2711: boot tested on RPi 4B v1.1 4G
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
(cherry-picked from commit f07e572f64)
88 lines
2.4 KiB
Diff
88 lines
2.4 KiB
Diff
From b2998ffa15aabea3292159ca20973f45ed9cb4b0 Mon Sep 17 00:00:00 2001
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From: bjorn <beikeland@gmail.com>
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Date: Thu, 7 May 2020 05:11:43 +0200
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Subject: [PATCH] overlays: Add spi0 overlay to support sc16is752
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Signed-off-by: Bjorn <beikeland@gmail.com>
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---
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arch/arm/boot/dts/overlays/Makefile | 1 +
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arch/arm/boot/dts/overlays/README | 8 ++++
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.../dts/overlays/sc16is752-spi0-overlay.dts | 44 +++++++++++++++++++
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3 files changed, 53 insertions(+)
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create mode 100644 arch/arm/boot/dts/overlays/sc16is752-spi0-overlay.dts
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--- a/arch/arm/boot/dts/overlays/Makefile
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+++ b/arch/arm/boot/dts/overlays/Makefile
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@@ -143,6 +143,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
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rra-digidac1-wm8741-audio.dtbo \
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sc16is750-i2c.dtbo \
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sc16is752-i2c.dtbo \
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+ sc16is752-spi0.dtbo \
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sc16is752-spi1.dtbo \
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sdhost.dtbo \
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sdio.dtbo \
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--- a/arch/arm/boot/dts/overlays/README
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+++ b/arch/arm/boot/dts/overlays/README
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@@ -2144,6 +2144,14 @@ Params: int_pin GPIO use
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xtal On-board crystal frequency (default 14745600)
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+Name: sc16is752-spi0
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+Info: Overlay for the NXP SC16IS752 Dual UART with SPI Interface
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+ Enables the chip on SPI0.
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+Load: dtoverlay=sc16is752-spi0,<param>=<val>
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+Params: int_pin GPIO used for IRQ (default 24)
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+ xtal On-board crystal frequency (default 14745600)
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+
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+
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Name: sc16is752-spi1
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Info: Overlay for the NXP SC16IS752 Dual UART with SPI Interface
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Enables the chip on SPI1.
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--- /dev/null
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+++ b/arch/arm/boot/dts/overlays/sc16is752-spi0-overlay.dts
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@@ -0,0 +1,44 @@
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+/dts-v1/;
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+/plugin/;
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+
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+/ {
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+ compatible = "brcm,bcm2835";
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+
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+ fragment@0 {
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+ target = <&spi0>;
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+ __overlay__ {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "okay";
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+
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+ sc16is752: sc16is752@0 {
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+ compatible = "nxp,sc16is752";
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+ reg = <0>; /* CE0 */
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+ clocks = <&sc16is752_clk>;
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+ interrupt-parent = <&gpio>;
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+ interrupts = <24 2>; /* IRQ_TYPE_EDGE_FALLING */
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+ #gpio-controller;
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+ #gpio-cells = <2>;
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+ spi-max-frequency = <4000000>;
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+
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+ sc16is752_clk: sc16is752_clk {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <14745600>;
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+ };
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+ };
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+ };
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+ };
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+
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+ fragment@1 {
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+ target = <&spidev0>;
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+ __overlay__ {
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+ status = "disabled";
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+ };
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+ };
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+
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+ __overrides__ {
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+ int_pin = <&sc16is752>,"interrupts:0";
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+ xtal = <&sc16is752_clk>, "clock-frequency:0";
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+ };
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+};
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