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2ad898e091
Removed upstreamed: generic/backport-6.1/789-STABLE-01-net-dsa-mt7530-prevent-possible-incorrect-XTAL-frequ.patch [1] generic/backport-6.1/789-STABLE-02-net-dsa-mt7530-fix-link-local-frames-that-ingress-vl.patch [2] generic/backport-6.1/789-STABLE-03-net-dsa-mt7530-fix-handling-of-all-link-local-frames.patch [3] generic/pending-6.1/735-net-mediatek-mtk_eth_soc-release-MAC_MCR_FORCE_LINK-.patch [4] generic/pending-6.1/736-net-ethernet-mtk_eth_soc-fix-PPE-hanging-issue.patch [5] Manual adjusted the following patches: mediatek/patches-6.1/100-dts-update-mt7622-rfb1.patch 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.83&id=be4512b9ac6fc53e1ca8daccbda84f643215c547 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.83&id=f1fa919ea59655f73cb3972264e157b8831ba546 3. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.83&id=86c0c154a759f2af9612a04bdf29110f02dce956 4. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.83&id=6b62bad2da1b338f452a9380639fc9b093d75a25 5. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.83&id=f78807362828ad01db2a9ed005bf79501b620f27 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
368 lines
9.1 KiB
Diff
368 lines
9.1 KiB
Diff
From f5d83b714e304d5f3229da434af2eeea033c4f5d Mon Sep 17 00:00:00 2001
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From: William Zhang <william.zhang@broadcom.com>
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Date: Mon, 6 Feb 2023 22:58:15 -0800
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Subject: [PATCH] arm64: dts: broadcom: bcmbca: Add spi controller node
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Add support for HSSPI controller in ARMv8 chip dts files.
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Signed-off-by: William Zhang <william.zhang@broadcom.com>
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Link: https://lore.kernel.org/r/20230207065826.285013-5-william.zhang@broadcom.com
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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---
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.../boot/dts/broadcom/bcmbca/bcm4908.dtsi | 18 +++++++++++++++++
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.../boot/dts/broadcom/bcmbca/bcm4912.dtsi | 20 +++++++++++++++++++
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.../boot/dts/broadcom/bcmbca/bcm63146.dtsi | 19 ++++++++++++++++++
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.../boot/dts/broadcom/bcmbca/bcm63158.dtsi | 19 ++++++++++++++++++
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.../boot/dts/broadcom/bcmbca/bcm6813.dtsi | 20 +++++++++++++++++++
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.../boot/dts/broadcom/bcmbca/bcm6856.dtsi | 18 +++++++++++++++++
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.../boot/dts/broadcom/bcmbca/bcm6858.dtsi | 18 +++++++++++++++++
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.../boot/dts/broadcom/bcmbca/bcm94908.dts | 4 ++++
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.../boot/dts/broadcom/bcmbca/bcm94912.dts | 4 ++++
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.../boot/dts/broadcom/bcmbca/bcm963146.dts | 4 ++++
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.../boot/dts/broadcom/bcmbca/bcm963158.dts | 4 ++++
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.../boot/dts/broadcom/bcmbca/bcm96813.dts | 4 ++++
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.../boot/dts/broadcom/bcmbca/bcm96856.dts | 4 ++++
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.../boot/dts/broadcom/bcmbca/bcm96858.dts | 4 ++++
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14 files changed, 160 insertions(+)
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--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
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+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
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@@ -107,6 +107,12 @@
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clock-frequency = <50000000>;
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clock-output-names = "periph";
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};
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+
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+ hsspi_pll: hsspi-pll {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <400000000>;
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+ };
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};
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soc {
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@@ -528,6 +534,18 @@
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#size-cells = <0>;
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};
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+ hsspi: spi@1000{
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "brcm,bcm4908-hsspi", "brcm,bcmbca-hsspi-v1.0";
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+ reg = <0x1000 0x600>;
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+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&hsspi_pll &hsspi_pll>;
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+ clock-names = "hsspi", "pll";
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+ num-cs = <8>;
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+ status = "disabled";
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+ };
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+
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nand-controller@1800 {
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#address-cells = <1>;
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#size-cells = <0>;
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--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
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+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
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@@ -79,6 +79,7 @@
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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+
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uart_clk: uart-clk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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@@ -86,6 +87,12 @@
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clock-div = <4>;
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clock-mult = <1>;
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};
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+
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+ hsspi_pll: hsspi-pll {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <200000000>;
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+ };
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};
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psci {
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@@ -117,6 +124,19 @@
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#size-cells = <1>;
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ranges = <0x0 0x0 0xff800000 0x800000>;
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+ hsspi: spi@1000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "brcm,bcm4912-hsspi", "brcm,bcmbca-hsspi-v1.1";
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+ reg = <0x1000 0x600>, <0x2610 0x4>;
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+ reg-names = "hsspi", "spim-ctrl";
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+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&hsspi_pll &hsspi_pll>;
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+ clock-names = "hsspi", "pll";
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+ num-cs = <8>;
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+ status = "disabled";
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+ };
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+
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uart0: serial@12000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x12000 0x1000>;
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--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
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+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
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@@ -60,6 +60,7 @@
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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+
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uart_clk: uart-clk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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@@ -67,6 +68,12 @@
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clock-div = <4>;
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clock-mult = <1>;
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};
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+
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+ hsspi_pll: hsspi-pll {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <200000000>;
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+ };
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};
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psci {
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@@ -99,6 +106,18 @@
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#size-cells = <1>;
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ranges = <0x0 0x0 0xff800000 0x800000>;
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+ hsspi: spi@1000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "brcm,bcm63146-hsspi", "brcm,bcmbca-hsspi-v1.0";
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+ reg = <0x1000 0x600>;
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+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&hsspi_pll &hsspi_pll>;
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+ clock-names = "hsspi", "pll";
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+ num-cs = <8>;
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+ status = "disabled";
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+ };
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+
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uart0: serial@12000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x12000 0x1000>;
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--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
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+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
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@@ -79,6 +79,7 @@
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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+
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uart_clk: uart-clk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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@@ -86,6 +87,12 @@
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clock-div = <4>;
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clock-mult = <1>;
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};
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+
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+ hsspi_pll: hsspi-pll {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <400000000>;
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+ };
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};
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psci {
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@@ -117,6 +124,18 @@
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#size-cells = <1>;
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ranges = <0x0 0x0 0xff800000 0x800000>;
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+ hsspi: spi@1000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "brcm,bcm63158-hsspi", "brcm,bcmbca-hsspi-v1.0";
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+ reg = <0x1000 0x600>;
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+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&hsspi_pll &hsspi_pll>;
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+ clock-names = "hsspi", "pll";
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+ num-cs = <8>;
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+ status = "disabled";
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+ };
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+
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uart0: serial@12000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x12000 0x1000>;
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--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
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+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
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@@ -79,6 +79,7 @@
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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+
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uart_clk: uart-clk {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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@@ -86,6 +87,12 @@
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clock-div = <4>;
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clock-mult = <1>;
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};
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+
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+ hsspi_pll: hsspi-pll {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <200000000>;
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+ };
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};
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psci {
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@@ -117,6 +124,19 @@
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#size-cells = <1>;
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ranges = <0x0 0x0 0xff800000 0x800000>;
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+ hsspi: spi@1000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "brcm,bcm6813-hsspi", "brcm,bcmbca-hsspi-v1.1";
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+ reg = <0x1000 0x600>, <0x2610 0x4>;
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+ reg-names = "hsspi", "spim-ctrl";
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+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&hsspi_pll &hsspi_pll>;
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+ clock-names = "hsspi", "pll";
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+ num-cs = <8>;
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+ status = "disabled";
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+ };
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+
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uart0: serial@12000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x12000 0x1000>;
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--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
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+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
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@@ -60,6 +60,12 @@
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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+
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+ hsspi_pll: hsspi-pll {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <400000000>;
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+ };
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};
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psci {
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@@ -100,5 +106,17 @@
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clock-names = "refclk";
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status = "disabled";
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};
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+
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+ hsspi: spi@1000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "brcm,bcm6856-hsspi", "brcm,bcmbca-hsspi-v1.0";
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+ reg = <0x1000 0x600>;
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+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&hsspi_pll &hsspi_pll>;
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+ clock-names = "hsspi", "pll";
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+ num-cs = <8>;
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+ status = "disabled";
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+ };
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};
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};
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--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
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+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
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@@ -78,6 +78,12 @@
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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+
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+ hsspi_pll: hsspi-pll {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <400000000>;
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+ };
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};
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psci {
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@@ -137,5 +143,17 @@
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clock-names = "refclk";
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status = "disabled";
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};
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+
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+ hsspi: spi@1000 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ compatible = "brcm,bcm6858-hsspi", "brcm,bcmbca-hsspi-v1.0";
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+ reg = <0x1000 0x600>;
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+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&hsspi_pll &hsspi_pll>;
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+ clock-names = "hsspi", "pll";
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+ num-cs = <8>;
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+ status = "disabled";
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+ };
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};
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};
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--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts
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+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts
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@@ -28,3 +28,7 @@
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&uart0 {
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status = "okay";
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};
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+
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+&hsspi {
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+ status = "okay";
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+};
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--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
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+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
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@@ -28,3 +28,7 @@
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&uart0 {
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status = "okay";
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};
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+
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+&hsspi {
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+ status = "okay";
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+};
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--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
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+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
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@@ -28,3 +28,7 @@
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&uart0 {
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status = "okay";
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};
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+
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+&hsspi {
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+ status = "okay";
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+};
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--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
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+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
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@@ -28,3 +28,7 @@
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&uart0 {
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status = "okay";
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};
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+
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+&hsspi {
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+ status = "okay";
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+};
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--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
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+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
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@@ -28,3 +28,7 @@
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&uart0 {
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status = "okay";
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};
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+
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+&hsspi {
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+ status = "okay";
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+};
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--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
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+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
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@@ -28,3 +28,7 @@
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&uart0 {
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status = "okay";
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};
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+
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+&hsspi {
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+ status = "okay";
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+};
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--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
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+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
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@@ -28,3 +28,7 @@
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&uart0 {
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status = "okay";
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};
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+
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+&hsspi {
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+ status = "okay";
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+};
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