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124 lines
2.0 KiB
Plaintext
124 lines
2.0 KiB
Plaintext
/dts-v1/;
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/include/ "mt7620a.dtsi"
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/ {
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compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
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model = "Ralink MT7620a + MT7610e evaluation board";
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memory@0 {
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reg = <0x0 0x2000000>;
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};
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palmbus@10000000 {
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sysc@0 {
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ralink,pinmux = "spi", "uartlite", "mdio", "wled", "ephy", "rgmii1", "rgmii2";
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ralink,gpiomux = "i2c", "jtag";
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ralink,uartmux = "gpio";
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ralink,wdtmux = <1>;
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};
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gpio0: gpio@600 {
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status = "okay";
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};
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spi@b00 {
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status = "okay";
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m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "en25q64";
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reg = <0 0>;
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linux,modalias = "m25p80", "en25q64";
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spi-max-frequency = <10000000>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x10000>;
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read-only;
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};
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factory: partition@40000 {
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label = "factory";
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reg = <0x40000 0x10000>;
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read-only;
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};
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partition@50000 {
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label = "firmware";
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reg = <0x50000 0x7b0000>;
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};
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};
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};
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};
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ethernet@10100000 {
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status = "okay";
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port@4 {
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compatible = "lantiq,mt7620a-gsw-port", "ralink,eth-port";
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reg = <4>;
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phy-mode = "rgmii";
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phy-handle = <&phy4>;
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};
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port@5 {
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compatible = "lantiq,mt7620a-gsw-port", "ralink,eth-port";
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reg = <5>;
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phy-mode = "rgmii";
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phy-handle = <&phy5>;
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};
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mdio-bus {
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status = "okay";
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phy4: ethernet-phy@4 {
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reg = <4>;
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phy-mode = "rgmii";
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};
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phy5: ethernet-phy@5 {
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reg = <5>;
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phy-mode = "rgmii";
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};
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};
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};
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gsw@10110000 {
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status = "okay";
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ralink,port4 = "gmac";
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};
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sdhci@10130000 {
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status = "okay";
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};
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pcie@10140000 {
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status = "okay";
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};
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gpio-keys-polled {
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compatible = "gpio-keys";
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#address-cells = <1>;
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#size-cells = <0>;
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poll-interval = <20>;
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s2 {
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label = "S2";
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gpios = <&gpio0 1 1>;
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linux,code = <0x100>;
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};
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s3 {
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label = "S3";
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gpios = <&gpio0 2 1>;
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linux,code = <0x101>;
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};
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};
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};
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