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047695a029
This reverts commit 51397d7d95.
There are some unresolved random crashes on WRT1900AC v1 that still need
to be sorted out
Signed-off-by: Felix Fietkau <nbd@nbd.name>
54 lines
1.5 KiB
Diff
54 lines
1.5 KiB
Diff
From: Marcin Wojtas <mw@semihalf.com>
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Date: Mon, 14 Mar 2016 09:38:59 +0100
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Subject: [PATCH] ARM: dts: armada-xp: add buffer manager nodes
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Armada XP network controller supports hardware buffer management (BM).
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Since it is now enabled in mvneta driver, appropriate nodes can be added
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to armada-xp.dtsi - for the actual common BM unit (bm@c0000) and its
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internal SRAM (bm-bppi), which is used for indirect access to buffer
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pointer ring residing in DRAM.
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Pools - ports mapping, bm-bppi entry in 'soc' node's ranges and optional
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parameters are supposed to be set in board files.
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Signed-off-by: Marcin Wojtas <mw@semihalf.com>
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Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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--- a/arch/arm/boot/dts/armada-xp.dtsi
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+++ b/arch/arm/boot/dts/armada-xp.dtsi
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@@ -253,6 +253,14 @@
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marvell,crypto-sram-size = <0x800>;
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};
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+ bm: bm@c0000 {
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+ compatible = "marvell,armada-380-neta-bm";
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+ reg = <0xc0000 0xac>;
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+ clocks = <&gateclk 13>;
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+ internal-mem = <&bm_bppi>;
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+ status = "disabled";
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+ };
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+
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xor@f0900 {
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compatible = "marvell,orion-xor";
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reg = <0xF0900 0x100
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@@ -291,6 +299,17 @@
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#size-cells = <1>;
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ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
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};
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+
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+ bm_bppi: bm-bppi {
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+ compatible = "mmio-sram";
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+ reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
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+ ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ clocks = <&gateclk 13>;
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+ no-memory-wc;
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+ status = "disabled";
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+ };
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};
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clocks {
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