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61ef5940f2
openwrt/target/linux/bcm63xx/patches-5.4/518-board_bcm6368.patch
Daniele Castro 61ef5940f2 bcm63xx: add support for ADB P.DG A4101N A-000-1A1-AE 
ADB P.DG A4101N A-000-1A1-AE has a similar PCB as the OpenWrt's ADB P.DG A4001N1
with LEDs connected to different GPIO PINs in active low configuration.

Hardware:
* Board ID: 96328avngv
* SoC: Broadcom BCM6328 (rev b0) @ 320MHz, CPU BMIPS4350
* RAM DDR2: 64 Mbyte - Winbond W9751G6KB-25
* Serial flash: 16 Mbyte - Winbond 25Q128BVFG
* Ethernet: 4x Ethernet 10/100 baseT
* Wifi 2.4GHz: Broadcom Corporation BCM43225 Wireless Network Adapter (rev 23)
* LEDs: 1x Power, 1x DSL, 1x Internet, 4x ETH, 1x USB, 1x WLAN, 1x WPS, 1x TEL
* Buttons: 1x Reset, 1x WPS, 1x unnamed
* UART: 1x TTL 115200n8, VCC RX TX GND, on J502 connector

Installation via CFE:
* Stock CFE has to be overwritten with a generic 6328 one that can upload
  .bin images with no signature check (cfe6328_configured.bin)
* Connect a serial port to the board
* Stop the cfe boot process after power on by pressing enter
* Set static IP 192.168.2.10 and subnet mask 255.255.255.0
* Navigate to http://192.168.2.50/
* Upload the OpenWrt image file

A4101N GPIO LAYOUT:

Power            always on
DSL              GPIO483(03)
Internet         GPIO491(11)
ETH1             GPIO505(25)
ETH2             GPIO506(26)
ETH3             GPIO507(27)
ETH4             GPIO508(28)
USB              GPIO490(10)
WLAN             controlled by BCM43225
WPS              GPIO489(09)
TEL              GPIO511(31)

Key RESET        GPIO503(23)
Key WPS          GPIO504(24)
Key unnamed      GPIO492(12)

Signed-off-by: Daniele Castro <danielecastro@hotmail.it>
[Amend commit description, DTS improvements, refresh patches]
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2020-12-06 16:24:04 +01:00

733 lines
15 KiB
Diff
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--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -13,6 +13,8 @@
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/pci_ids.h>
+#include <linux/platform_data/b53.h>
+#include <linux/spi/spi.h>
#include <asm/addrspace.h>
#include <bcm63xx_board.h>
#include <bcm63xx_cpu.h>
@@ -1941,6 +1943,648 @@ static struct board_info __initdata boar
#endif /* CONFIG_BCM63XX_CPU_6362 */
/*
+ * known 6368 boards
+ */
+#ifdef CONFIG_BCM63XX_CPU_6368
+static struct board_info __initdata board_96368mvngr = {
+ .name = "96368MVNgr",
+ .expected_cpu_id = 0x6368,
+
+ .has_pci = 1,
+ .has_ohci0 = 1,
+ .has_ehci0 = 1,
+
+ .has_enetsw = 1,
+ .enetsw = {
+ .used_ports = {
+ [0] = {
+ .used = 1,
+ .phy_id = 1,
+ .name = "port1",
+ },
+ [1] = {
+ .used = 1,
+ .phy_id = 2,
+ .name = "port2",
+ },
+ [2] = {
+ .used = 1,
+ .phy_id = 3,
+ .name = "port3",
+ },
+ [3] = {
+ .used = 1,
+ .phy_id = 4,
+ .name = "port4",
+ },
+ },
+ },
+};
+
+static struct board_info __initdata board_96368mvwg = {
+ .name = "96368MVWG",
+ .expected_cpu_id = 0x6368,
+
+ .has_pci = 1,
+ .has_ohci0 = 1,
+ .has_ehci0 = 1,
+
+ .has_usbd = 1,
+ .usbd = {
+ .use_fullspeed = 0,
+ .port_no = 0,
+ },
+
+ .has_enetsw = 1,
+ .enetsw = {
+ .used_ports = {
+ [1] = {
+ .used = 1,
+ .phy_id = 2,
+ .name = "port1",
+ },
+ [2] = {
+ .used = 1,
+ .phy_id = 3,
+ .name = "port2",
+ },
+ [4] = {
+ .used = 1,
+ .phy_id = 0x12,
+ .name = "port0",
+ },
+ [5] = {
+ .used = 1,
+ .phy_id = 0x11,
+ .name = "port3",
+ },
+ },
+ },
+};
+
+static struct board_info __initdata board_AV4202N = {
+ .name = "96368_Swiss_S1",
+ .expected_cpu_id = 0x6368,
+
+ .has_pci = 1,
+ .has_ohci0 = 1,
+ .has_ehci0 = 1,
+ .num_usbh_ports = 2,
+
+ .has_enetsw = 1,
+ .enetsw = {
+ .used_ports = {
+ [0] = {
+ .used = 1,
+ .phy_id = 1,
+ .name = "port1",
+ },
+ [1] = {
+ .used = 1,
+ .phy_id = 2,
+ .name = "port2",
+ },
+ [2] = {
+ .used = 1,
+ .phy_id = 3,
+ .name = "port3",
+ },
+ [3] = {
+ .used = 1,
+ .phy_id = 4,
+ .name = "port4",
+ },
+ },
+ },
+
+ .use_fallback_sprom = 1,
+ .fallback_sprom = {
+ .type = SPROM_BCM4322,
+ .pci_bus = 0,
+ .pci_dev = 1,
+ },
+};
+
+static struct board_info __initdata board_DGND3700v1_3800B = {
+ .name = "DGND3700v1_3800B",
+ .expected_cpu_id = 0x6368,
+
+ .has_pci = 1,
+ .has_ohci0 = 1,
+ .has_ehci0 = 1,
+ .num_usbh_ports = 2,
+
+ .has_enetsw = 1,
+ .enetsw = {
+ .used_ports = {
+ [5] = {
+ .used = 1,
+ .phy_id = 0xff,
+ .bypass_link = 1,
+ .force_speed = 1000,
+ .force_duplex_full = 1,
+ .name = "RGMII",
+ },
+ },
+ },
+};
+
+static struct sprom_fixup __initdata EVG2000_fixups[] = {
+ { .offset = 219, .value = 0xec08 },
+};
+
+static struct board_info __initdata board_EVG2000 = {
+ .name = "96369PVG",
+ .expected_cpu_id = 0x6368,
+
+ .has_pci = 1,
+ .has_ohci0 = 1,
+ .has_ehci0 = 1,
+ .num_usbh_ports = 2,
+
+ .has_enetsw = 1,
+ .enetsw = {
+ .used_ports = {
+ [5] = {
+ .used = 1,
+ .phy_id = 0xff,
+ .bypass_link = 1,
+ .force_speed = 1000,
+ .force_duplex_full = 1,
+ .name = "RGMII",
+ },
+ },
+ },
+
+ .use_fallback_sprom = 1,
+ .fallback_sprom = {
+ .type = SPROM_BCM4322,
+ .pci_bus = 0,
+ .pci_dev = 1,
+ .board_fixups = EVG2000_fixups,
+ .num_board_fixups = ARRAY_SIZE(EVG2000_fixups),
+ },
+};
+
+static struct board_info __initdata board_HG622 = {
+ .name = "96368MVWG_hg622",
+ .expected_cpu_id = 0x6368,
+
+ .has_pci = 1,
+ .has_ohci0 = 1,
+ .has_ehci0 = 1,
+ .num_usbh_ports = 2,
+
+ .has_caldata = 1,
+ .caldata = {
+ {
+ .vendor = PCI_VENDOR_ID_RALINK,
+ .caldata_offset = 0xfa0000,
+ .slot = 1,
+ .eeprom = "rt2x00.eeprom",
+ },
+ },
+
+ .has_enetsw = 1,
+ .enetsw = {
+ .used_ports = {
+ [0] = {
+ .used = 1,
+ .phy_id = 1,
+ .name = "port1",
+ },
+ [1] = {
+ .used = 1,
+ .phy_id = 2,
+ .name = "port2",
+ },
+ [2] = {
+ .used = 1,
+ .phy_id = 3,
+ .name = "port3",
+ },
+ [3] = {
+ .used = 1,
+ .phy_id = 4,
+ .name = "port4",
+ },
+ },
+ },
+};
+
+static struct board_info __initdata board_HG655b = {
+ .name = "HW65x",
+ .expected_cpu_id = 0x6368,
+
+ .has_pci = 1,
+ .has_ohci0 = 1,
+ .has_ehci0 = 1,
+ .num_usbh_ports = 2,
+
+ .has_caldata = 1,
+ .caldata = {
+ {
+ .vendor = PCI_VENDOR_ID_RALINK,
+ .caldata_offset = 0x7c0000,
+ .slot = 1,
+ .eeprom = "rt2x00.eeprom",
+ },
+ },
+
+ .has_enetsw = 1,
+ .enetsw = {
+ .used_ports = {
+ [0] = {
+ .used = 1,
+ .phy_id = 1,
+ .name = "port1",
+ },
+ [1] = {
+ .used = 1,
+ .phy_id = 2,
+ .name = "port2",
+ },
+ [2] = {
+ .used = 1,
+ .phy_id = 3,
+ .name = "port3",
+ },
+ [3] = {
+ .used = 1,
+ .phy_id = 4,
+ .name = "port4",
+ },
+ },
+ },
+};
+
+static struct board_info __initdata board_P870HW51A_V2 = {
+ .name = "P870HW-51a_v2",
+ .expected_cpu_id = 0x6368,
+
+ .has_pci = 1,
+ .has_ohci0 = 1,
+ .has_ehci0 = 1,
+
+ .has_enetsw = 1,
+ .enetsw = {
+ .used_ports = {
+ [0] = {
+ .used = 1,
+ .phy_id = 1,
+ .name = "port1",
+ },
+ [1] = {
+ .used = 1,
+ .phy_id = 2,
+ .name = "port2",
+ },
+ [2] = {
+ .used = 1,
+ .phy_id = 3,
+ .name = "port3",
+ },
+ [3] = {
+ .used = 1,
+ .phy_id = 4,
+ .name = "port4",
+ },
+ },
+ },
+
+ .use_fallback_sprom = 1,
+ .fallback_sprom = {
+ .type = SPROM_BCM4318,
+ .pci_bus = 0,
+ .pci_dev = 1,
+ },
+};
+
+static struct board_info __initdata board_R1000H = {
+ .name = "R1000H",
+ .expected_cpu_id = 0x6368,
+
+ .has_pci = 1,
+ .has_ohci0 = 1,
+ .has_ehci0 = 1,
+
+ .has_enetsw = 1,
+ .enetsw = {
+ .used_ports = {
+ [5] = {
+ .used = 1,
+ .phy_id = 0xff,
+ .bypass_link = 1,
+ .force_speed = 1000,
+ .force_duplex_full = 1,
+ .name = "RGMII",
+ },
+ },
+ },
+};
+
+static struct sprom_fixup __initdata vh4032n_fixups[] = {
+ { .offset = 2, .value = 0x04d2 },
+ { .offset = 4, .value = 0x4350 },
+ { .offset = 65, .value = 0x1300 },
+ { .offset = 68, .value = 0x0402 },
+ { .offset = 70, .value = 0x0090 },
+ { .offset = 71, .value = 0x4c19 },
+ { .offset = 72, .value = 0x2345 },
+ { .offset = 87, .value = 0x0315 },
+ { .offset = 88, .value = 0x0315 },
+ { .offset = 96, .value = 0x2048 },
+ { .offset = 97, .value = 0xfed7 },
+ { .offset = 98, .value = 0x15a6 },
+ { .offset = 99, .value = 0xfaee },
+ { .offset = 100, .value = 0x3e3a },
+ { .offset = 101, .value = 0x3a36 },
+ { .offset = 102, .value = 0xff7f },
+ { .offset = 103, .value = 0x11b9 },
+ { .offset = 104, .value = 0xfc53 },
+ { .offset = 105, .value = 0xffe6 },
+ { .offset = 106, .value = 0xfdd2 },
+ { .offset = 107, .value = 0xfe49 },
+ { .offset = 108, .value = 0xff6a },
+ { .offset = 109, .value = 0x136e },
+ { .offset = 110, .value = 0xfbed },
+ { .offset = 111, .value = 0x0000 },
+ { .offset = 112, .value = 0x2048 },
+ { .offset = 113, .value = 0xfee2 },
+ { .offset = 114, .value = 0x15e5 },
+ { .offset = 115, .value = 0xfaed },
+ { .offset = 116, .value = 0x3e3a },
+ { .offset = 117, .value = 0x3a36 },
+ { .offset = 118, .value = 0xffc8 },
+ { .offset = 119, .value = 0x12b8 },
+ { .offset = 120, .value = 0xfca1 },
+ { .offset = 121, .value = 0xff9b },
+ { .offset = 122, .value = 0x122a },
+ { .offset = 123, .value = 0xfcc8 },
+ { .offset = 124, .value = 0xff95 },
+ { .offset = 125, .value = 0x146b },
+ { .offset = 126, .value = 0xfbba },
+ { .offset = 127, .value = 0x0000 },
+ { .offset = 161, .value = 0x0000 },
+ { .offset = 162, .value = 0x0000 },
+ { .offset = 169, .value = 0x0000 },
+ { .offset = 170, .value = 0x0000 },
+ { .offset = 171, .value = 0x0000 },
+ { .offset = 172, .value = 0x0000 },
+ { .offset = 173, .value = 0x0000 },
+ { .offset = 174, .value = 0x0000 },
+ { .offset = 175, .value = 0x0000 },
+ { .offset = 176, .value = 0x0000 },
+ { .offset = 219, .value = 0x1108 },
+};
+
+static struct board_info __initdata board_VH4032N = {
+ .name = "VH4032N",
+ .expected_cpu_id = 0x6368,
+
+ .has_pci = 1,
+ .has_ohci0 = 1,
+ .has_ehci0 = 1,
+ .num_usbh_ports = 2,
+
+ .has_enetsw = 1,
+ .enetsw = {
+ .used_ports = {
+ [0] = {
+ .used = 1,
+ .phy_id = 1,
+ .name = "LAN4",
+ },
+ [1] = {
+ .used = 1,
+ .phy_id = 2,
+ .name = "LAN3",
+ },
+ [2] = {
+ .used = 1,
+ .phy_id = 3,
+ .name = "LAN2",
+ },
+ [3] = {
+ .used = 1,
+ .phy_id = 4,
+ .name = "LAN1",
+ },
+ },
+ },
+
+ .use_fallback_sprom = 1,
+ .fallback_sprom = {
+ .type = SPROM_BCM43222,
+ .pci_bus = 0,
+ .pci_dev = 1,
+ .board_fixups = vh4032n_fixups,
+ .num_board_fixups = ARRAY_SIZE(vh4032n_fixups),
+ },
+};
+
+static struct sprom_fixup __initdata vr3025u_fixups[] = {
+ { .offset = 97, .value = 0xfeb3 },
+ { .offset = 98, .value = 0x1618 },
+ { .offset = 99, .value = 0xfab0 },
+ { .offset = 113, .value = 0xfed1 },
+ { .offset = 114, .value = 0x1609 },
+ { .offset = 115, .value = 0xfad9 },
+};
+
+static struct board_info __initdata board_VR3025u = {
+ .name = "96368M-1541N",
+ .expected_cpu_id = 0x6368,
+
+ .has_pci = 1,
+ .has_ohci0 = 1,
+ .has_ehci0 = 1,
+
+ .has_enetsw = 1,
+ .enetsw = {
+ .used_ports = {
+ [0] = {
+ .used = 1,
+ .phy_id = 1,
+ .name = "port1",
+ },
+ [1] = {
+ .used = 1,
+ .phy_id = 2,
+ .name = "port2",
+ },
+ [2] = {
+ .used = 1,
+ .phy_id = 3,
+ .name = "port3",
+ },
+ [3] = {
+ .used = 1,
+ .phy_id = 4,
+ .name = "port4",
+ },
+ },
+ },
+
+ .use_fallback_sprom = 1,
+ .fallback_sprom = {
+ .type = SPROM_BCM43222,
+ .pci_bus = 0,
+ .pci_dev = 1,
+ .board_fixups = vr3025u_fixups,
+ .num_board_fixups = ARRAY_SIZE(vr3025u_fixups),
+ },
+};
+
+static struct sprom_fixup __initdata vr3025un_fixups[] = {
+ { .offset = 97, .value = 0xfeb3 },
+ { .offset = 98, .value = 0x1618 },
+ { .offset = 99, .value = 0xfab0 },
+ { .offset = 113, .value = 0xfed1 },
+ { .offset = 114, .value = 0x1609 },
+ { .offset = 115, .value = 0xfad9 },
+};
+
+static struct board_info __initdata board_VR3025un = {
+ .name = "96368M-1341N",
+ .expected_cpu_id = 0x6368,
+
+ .has_pci = 1,
+ .has_ohci0 = 1,
+ .has_ehci0 = 1,
+
+ .has_enetsw = 1,
+ .enetsw = {
+ .used_ports = {
+ [0] = {
+ .used = 1,
+ .phy_id = 1,
+ .name = "port1",
+ },
+ [1] = {
+ .used = 1,
+ .phy_id = 2,
+ .name = "port2",
+ },
+ [2] = {
+ .used = 1,
+ .phy_id = 3,
+ .name = "port3",
+ },
+ [3] = {
+ .used = 1,
+ .phy_id = 4,
+ .name = "port4",
+ },
+ },
+ },
+
+ .use_fallback_sprom = 1,
+ .fallback_sprom = {
+ .type = SPROM_BCM43222,
+ .pci_bus = 0,
+ .pci_dev = 1,
+ .board_fixups = vr3025un_fixups,
+ .num_board_fixups = ARRAY_SIZE(vr3025un_fixups),
+ },
+};
+
+static struct sprom_fixup __initdata vr3026e_fixups[] = {
+ { .offset = 97, .value = 0xfeb3 },
+ { .offset = 98, .value = 0x1618 },
+ { .offset = 99, .value = 0xfab0 },
+ { .offset = 113, .value = 0xfed1 },
+ { .offset = 114, .value = 0x1609 },
+ { .offset = 115, .value = 0xfad9 },
+};
+
+static struct board_info __initdata board_VR3026e = {
+ .name = "96368MT-1341N1",
+ .expected_cpu_id = 0x6368,
+
+ .has_pci = 1,
+ .has_ohci0 = 1,
+ .has_ehci0 = 1,
+
+ .has_enetsw = 1,
+ .enetsw = {
+ .used_ports = {
+ [0] = {
+ .used = 1,
+ .phy_id = 1,
+ .name = "port1",
+ },
+ [1] = {
+ .used = 1,
+ .phy_id = 2,
+ .name = "port2",
+ },
+ [2] = {
+ .used = 1,
+ .phy_id = 3,
+ .name = "port3",
+ },
+ [3] = {
+ .used = 1,
+ .phy_id = 4,
+ .name = "port4",
+ },
+ },
+ },
+
+ .use_fallback_sprom = 1,
+ .fallback_sprom = {
+ .type = SPROM_BCM43222,
+ .pci_bus = 0,
+ .pci_dev = 1,
+ .board_fixups = vr3026e_fixups,
+ .num_board_fixups = ARRAY_SIZE(vr3026e_fixups),
+ },
+};
+
+static struct sprom_fixup __initdata wap5813n_fixups[] = {
+ { .offset = 97, .value = 0xfeed },
+ { .offset = 98, .value = 0x15d1 },
+ { .offset = 99, .value = 0xfb0d },
+ { .offset = 113, .value = 0xfef7 },
+ { .offset = 114, .value = 0x15f7 },
+ { .offset = 115, .value = 0xfb1a },
+};
+
+static struct board_info __initdata board_WAP5813n = {
+ .name = "96369R-1231N",
+ .expected_cpu_id = 0x6368,
+
+ .has_pci = 1,
+ .has_ohci0 = 1,
+ .has_ehci0 = 1,
+
+ .has_enetsw = 1,
+ .enetsw = {
+ .used_ports = {
+ [4] = {
+ .used = 1,
+ .phy_id = 0xff,
+ .bypass_link = 1,
+ .force_speed = 1000,
+ .force_duplex_full = 1,
+ .name = "RGMII",
+ },
+ },
+ },
+
+ .use_fallback_sprom = 1,
+ .fallback_sprom = {
+ .type = SPROM_BCM43222,
+ .pci_bus = 0,
+ .pci_dev = 1,
+ .board_fixups = wap5813n_fixups,
+ .num_board_fixups = ARRAY_SIZE(wap5813n_fixups),
+ },
+};
+#endif /* CONFIG_BCM63XX_CPU_6368 */
+
+/*
* all boards
*/
static const struct board_info __initconst *bcm963xx_boards[] = {
@@ -2026,6 +2670,22 @@ static const struct board_info __initcon
&board_hg253s_v2,
&board_nb6,
#endif /* CONFIG_BCM63XX_CPU_6362 */
+#ifdef CONFIG_BCM63XX_CPU_6368
+ &board_96368mvngr,
+ &board_96368mvwg,
+ &board_AV4202N,
+ &board_DGND3700v1_3800B,
+ &board_EVG2000,
+ &board_HG622,
+ &board_HG655b,
+ &board_P870HW51A_V2,
+ &board_R1000H,
+ &board_VH4032N,
+ &board_VR3025u,
+ &board_VR3025un,
+ &board_VR3026e,
+ &board_WAP5813n,
+#endif /* CONFIG_BCM63XX_CPU_6368 */
};
static struct of_device_id const bcm963xx_boards_dt[] = {
@@ -2124,6 +2784,20 @@ static struct of_device_id const bcm963x
{ .compatible = "sfr,neufbox-6-sercomm-r0", .data = &board_nb6, },
#endif /* CONFIG_BCM63XX_CPU_6362 */
#ifdef CONFIG_BCM63XX_CPU_6368
+ { .compatible = "actiontec,r1000h", .data = &board_R1000H, },
+ { .compatible = "adb,av4202n", .data = &board_AV4202N, },
+ { .compatible = "brcm,bcm96368mvngr", .data = &board_96368mvngr, },
+ { .compatible = "brcm,bcm96368mvwg", .data = &board_96368mvwg, },
+ { .compatible = "comtrend,vr-3025u", .data = &board_VR3025u, },
+ { .compatible = "comtrend,vr-3025un", .data = &board_VR3025un, },
+ { .compatible = "comtrend,vr-3026e", .data = &board_VR3026e, },
+ { .compatible = "comtrend,wap-5813n", .data = &board_WAP5813n, },
+ { .compatible = "huawei,echolife-hg622", .data = &board_HG622, },
+ { .compatible = "huawei,echolife-hg655b", .data = &board_HG655b, },
+ { .compatible = "netgear,dgnd3700-v1", .data = &board_DGND3700v1_3800B, },
+ { .compatible = "netgear,evg2000", .data = &board_EVG2000, },
+ { .compatible = "observa,vh4032n", .data = &board_VH4032N, },
+ { .compatible = "zyxel,p870hw-51a-v2", .data = &board_P870HW51A_V2, },
#endif /* CONFIG_BCM63XX_CPU_6368 */
#ifdef CONFIG_BCM63XX_CPU_63268
#endif /* CONFIG_BCM63XX_CPU_63268 */
--- a/arch/mips/bcm63xx/boards/board_common.c
+++ b/arch/mips/bcm63xx/boards/board_common.c
@@ -81,12 +81,25 @@ void __init board_early_setup(const stru
bcm63xx_pci_enabled = 1;
if (BCMCPU_IS_6348())
val |= GPIO_MODE_6348_G2_PCI;
+
+ if (BCMCPU_IS_6368())
+ val |= GPIO_MODE_6368_PCI_REQ1 |
+ GPIO_MODE_6368_PCI_GNT1 |
+ GPIO_MODE_6368_PCI_INTB |
+ GPIO_MODE_6368_PCI_REQ0 |
+ GPIO_MODE_6368_PCI_GNT0;
}
#endif
if (board.has_pccard) {
if (BCMCPU_IS_6348())
val |= GPIO_MODE_6348_G1_MII_PCCARD;
+
+ if (BCMCPU_IS_6368())
+ val |= GPIO_MODE_6368_PCMCIA_CD1 |
+ GPIO_MODE_6368_PCMCIA_CD2 |
+ GPIO_MODE_6368_PCMCIA_VS1 |
+ GPIO_MODE_6368_PCMCIA_VS2;
}
if (board.has_enet0 && !board.enet0.use_internal_phy) {
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