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88ba41453d
Refresh patches. Remove upstreamed patches: - backport/080-v4.15-0001-arch-define-weak-abort.patch - backport/081-v4.15-0002-kernel-exit.c-export-abort-to-modules.patch Update patch that no longer applies: pending/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch Fixes CVE-2017-8824. Compile-tested: octeon, x86/64. Runtime-tested: octeon, x86/64. Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
111 lines
3.4 KiB
Diff
111 lines
3.4 KiB
Diff
From b1e7791e688620c9bb8476ac2d0bc99abeb7f825 Mon Sep 17 00:00:00 2001
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From: Tim Harvey <tharvey@gateworks.com>
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Date: Fri, 29 Dec 2017 16:48:04 -0800
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Subject: [PATCH] net: thunderx: workaround BGX TX Underflow issue
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While it is not yet understood why a TX underflow can easily occur
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for SGMII interfaces resulting in a TX wedge. It has been found that
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disabling/re-enabling the LMAC resolves the issue.
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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---
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drivers/net/ethernet/cavium/thunder/thunder_bgx.c | 54 +++++++++++++++++++++++
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drivers/net/ethernet/cavium/thunder/thunder_bgx.h | 9 ++++
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2 files changed, 63 insertions(+)
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--- a/drivers/net/ethernet/cavium/thunder/thunder_bgx.c
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+++ b/drivers/net/ethernet/cavium/thunder/thunder_bgx.c
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@@ -1344,6 +1344,54 @@ static int bgx_init_phy(struct bgx *bgx)
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return bgx_init_of_phy(bgx);
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}
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+static irqreturn_t bgx_intr_handler(int irq, void *data)
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+{
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+ struct bgx *bgx = (struct bgx *)data;
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+ struct device *dev = &bgx->pdev->dev;
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+ u64 status, val;
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+ int lmac;
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+
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+ for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
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+ status = bgx_reg_read(bgx, lmac, BGX_GMP_GMI_TXX_INT);
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+ if (status & GMI_TXX_INT_UNDFLW) {
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+ dev_err(dev, "BGX%d lmac%d UNDFLW\n", bgx->bgx_id,
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+ lmac);
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+ val = bgx_reg_read(bgx, lmac, BGX_CMRX_CFG);
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+ val &= ~CMR_EN;
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+ bgx_reg_write(bgx, lmac, BGX_CMRX_CFG, val);
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+ val |= CMR_EN;
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+ bgx_reg_write(bgx, lmac, BGX_CMRX_CFG, val);
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+ }
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+ /* clear interrupts */
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+ bgx_reg_write(bgx, lmac, BGX_GMP_GMI_TXX_INT, status);
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+ }
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+
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+ return IRQ_HANDLED;
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+}
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+
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+static int bgx_register_intr(struct pci_dev *pdev)
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+{
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+ struct bgx *bgx = pci_get_drvdata(pdev);
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+ struct device *dev = &pdev->dev;
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+ int num_vec, ret;
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+ char irq_name[32];
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+
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+ /* Enable MSI-X */
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+ num_vec = pci_msix_vec_count(pdev);
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+ ret = pci_alloc_irq_vectors(pdev, num_vec, num_vec, PCI_IRQ_MSIX);
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+ if (ret < 0) {
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+ dev_err(dev, "Req for #%d msix vectors failed\n", num_vec);
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+ return 1;
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+ }
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+ sprintf(irq_name, "BGX%d", bgx->bgx_id);
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+ ret = request_irq(pci_irq_vector(pdev, GMPX_GMI_TX_INT),
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+ bgx_intr_handler, 0, irq_name, bgx);
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+ if (ret)
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+ return 1;
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+
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+ return 0;
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+}
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+
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static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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int err;
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@@ -1414,6 +1462,8 @@ static int bgx_probe(struct pci_dev *pde
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xcv_init_hw(bgx->phy_mode);
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bgx_init_hw(bgx);
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+ bgx_register_intr(pdev);
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+
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/* Enable all LMACs */
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for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
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err = bgx_lmac_enable(bgx, lmac);
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@@ -1424,6 +1474,10 @@ static int bgx_probe(struct pci_dev *pde
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bgx_lmac_disable(bgx, --lmac);
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goto err_enable;
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}
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+
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+ /* enable TX FIFO Underflow interrupt */
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+ bgx_reg_modify(bgx, lmac, BGX_GMP_GMI_TXX_INT_ENA_W1S,
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+ GMI_TXX_INT_UNDFLW);
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}
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return 0;
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--- a/drivers/net/ethernet/cavium/thunder/thunder_bgx.h
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+++ b/drivers/net/ethernet/cavium/thunder/thunder_bgx.h
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@@ -179,6 +179,15 @@
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#define BGX_GMP_GMI_TXX_BURST 0x38228
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#define BGX_GMP_GMI_TXX_MIN_PKT 0x38240
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#define BGX_GMP_GMI_TXX_SGMII_CTL 0x38300
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+#define BGX_GMP_GMI_TXX_INT 0x38500
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+#define BGX_GMP_GMI_TXX_INT_W1S 0x38508
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+#define BGX_GMP_GMI_TXX_INT_ENA_W1C 0x38510
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+#define BGX_GMP_GMI_TXX_INT_ENA_W1S 0x38518
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+#define GMI_TXX_INT_PTP_LOST BIT_ULL(4)
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+#define GMI_TXX_INT_LATE_COL BIT_ULL(3)
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+#define GMI_TXX_INT_XSDEF BIT_ULL(2)
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+#define GMI_TXX_INT_XSCOL BIT_ULL(1)
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+#define GMI_TXX_INT_UNDFLW BIT_ULL(0)
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#define BGX_MSIX_VEC_0_29_ADDR 0x400000 /* +(0..29) << 4 */
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#define BGX_MSIX_VEC_0_29_CTL 0x400008
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