mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-23 07:22:33 +00:00
430 lines
11 KiB
Diff
430 lines
11 KiB
Diff
--- a/arch/arm/Kconfig
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+++ b/arch/arm/Kconfig
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@@ -375,6 +375,7 @@ config ARCH_CNS3XXX
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select PCI_DOMAINS if PCI
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select HAVE_ARM_TWD
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select HAVE_SMP
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+ select FIQ
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help
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Support for Cavium Networks CNS3XXX platform.
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--- a/arch/arm/kernel/fiq.c
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+++ b/arch/arm/kernel/fiq.c
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@@ -49,6 +49,8 @@
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static unsigned long no_fiq_insn;
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+unsigned int fiq_number[2] = {0, 0};
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+
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/* Default reacquire function
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* - we always relinquish FIQ control
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* - we always reacquire FIQ control
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@@ -70,9 +72,12 @@ static struct fiq_handler *current_fiq =
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int show_fiq_list(struct seq_file *p, int prec)
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{
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- if (current_fiq != &default_owner)
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- seq_printf(p, "%*s: %s\n", prec, "FIQ",
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- current_fiq->name);
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+ if (current_fiq != &default_owner) {
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+ seq_printf(p, "%*s: ", prec, "FIQ");
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+ seq_printf(p, "%10u ", fiq_number[0]);
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+ seq_printf(p, "%10u ", fiq_number[1]);
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+ seq_printf(p, " %s\n", current_fiq->name);
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+ }
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return 0;
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}
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--- a/arch/arm/kernel/smp.c
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+++ b/arch/arm/kernel/smp.c
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@@ -400,13 +400,13 @@ void show_ipi_list(struct seq_file *p, i
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unsigned int cpu, i;
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for (i = 0; i < NR_IPI; i++) {
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- seq_printf(p, "%*s%u: ", prec - 1, "IPI", i);
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+ seq_printf(p, "%*s%u:", prec - 1, "IPI", i);
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for_each_present_cpu(cpu)
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seq_printf(p, "%10u ",
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__get_irq_stat(cpu, ipi_irqs[i]));
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- seq_printf(p, " %s\n", ipi_types[i]);
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+ seq_printf(p, " %s\n", ipi_types[i]);
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}
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}
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--- a/arch/arm/mach-cns3xxx/Makefile
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+++ b/arch/arm/mach-cns3xxx/Makefile
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@@ -2,6 +2,6 @@ obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm
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obj-$(CONFIG_PCI) += pcie.o
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obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
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obj-$(CONFIG_MACH_GW2388) += laguna.o
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-obj-$(CONFIG_SMP) += platsmp.o headsmp.o
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+obj-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o
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obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
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--- /dev/null
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+++ b/arch/arm/mach-cns3xxx/cns3xxx_fiq.S
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@@ -0,0 +1,97 @@
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+/*
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+ * linux/arch/arm/lib/floppydma.S
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+ *
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+ * Copyright (C) 1995, 1996 Russell King
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+#include <linux/linkage.h>
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+#include <asm/assembler.h>
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+#include <asm/asm-offsets.h>
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+
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+#define D_CACHE_LINE_SIZE 32
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+
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+ .text
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+
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+/*
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+ * R8 - DMA Start Address
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+ * R9 - DMA Length
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+ * R10 - DMA Direction
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+ * R11 - DMA type
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+ * R12 - fiq_buffer Address
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+ * R13 - DMA type Address
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+*/
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+
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+ .global cns3xxx_fiq_end
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+ENTRY(cns3xxx_fiq_start)
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+ mov r8, #0
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+ str r8, [r13]
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+
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+ ldr r9, [r12]
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+ ldr r8, [r9]
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+ add r8, r8, #1
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+ str r8, [r9]
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+
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+ ldmib r12, {r8, r9, r10}
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+ and r11, r10, #0x3000000
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+ and r10, r10, #0xff
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+
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+ teq r11, #0x1000000
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+ beq cns3xxx_dma_map_area
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+ teq r11, #0x2000000
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+ beq cns3xxx_dma_unmap_area
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+ b cns3xxx_dma_flush_range
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+
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+cns3xxx_fiq_exit:
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+ mov r8, #0
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+ str r8, [r12, #12]
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+ mcr p15, 0, r8, c7, c10, 4 @ drain write buffer
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+ subs pc, lr, #4
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+
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+cns3xxx_dma_map_area:
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+ add r9, r9, r8
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+ teq r10, #DMA_FROM_DEVICE
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+ beq cns3xxx_dma_inv_range
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+ b cns3xxx_dma_clean_range
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+
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+cns3xxx_dma_unmap_area:
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+ add r9, r9, r8
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+ teq r10, #DMA_TO_DEVICE
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+ bne cns3xxx_dma_inv_range
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+ b cns3xxx_fiq_exit
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+
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+cns3xxx_dma_flush_range:
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+ bic r8, r8, #D_CACHE_LINE_SIZE - 1
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+1:
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+ mcr p15, 0, r8, c7, c14, 1 @ clean & invalidate D line
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+ add r8, r8, #D_CACHE_LINE_SIZE
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+ cmp r8, r9
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+ blo 1b
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+ b cns3xxx_fiq_exit
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+
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+cns3xxx_dma_clean_range:
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+ bic r8, r8, #D_CACHE_LINE_SIZE - 1
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+1:
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+ mcr p15, 0, r8, c7, c10, 1 @ clean D line
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+ add r8, r8, #D_CACHE_LINE_SIZE
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+ cmp r8, r9
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+ blo 1b
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+ b cns3xxx_fiq_exit
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+
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+cns3xxx_dma_inv_range:
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+ tst r8, #D_CACHE_LINE_SIZE - 1
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+ bic r8, r8, #D_CACHE_LINE_SIZE - 1
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+ mcrne p15, 0, r8, c7, c10, 1 @ clean D line
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+ tst r9, #D_CACHE_LINE_SIZE - 1
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+ bic r9, r9, #D_CACHE_LINE_SIZE - 1
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+ mcrne p15, 0, r9, c7, c14, 1 @ clean & invalidate D line
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+1:
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+ mcr p15, 0, r8, c7, c6, 1 @ invalidate D line
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+ add r8, r8, #D_CACHE_LINE_SIZE
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+ cmp r8, r9
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+ blo 1b
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+ b cns3xxx_fiq_exit
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+
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+cns3xxx_fiq_end:
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--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
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+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
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@@ -294,6 +294,7 @@
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#define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100)
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#define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100)
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+#define MISC_FIQ_CPU(x) MISC_MEM_MAP(0xA58 - (x) * 0x4)
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/*
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* Power management and clock control
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*/
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--- a/arch/arm/mach-cns3xxx/include/mach/irqs.h
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+++ b/arch/arm/mach-cns3xxx/include/mach/irqs.h
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@@ -14,6 +14,7 @@
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#define IRQ_LOCALTIMER 29
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#define IRQ_LOCALWDOG 30
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#define IRQ_TC11MP_GIC_START 32
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+#define FIQ_START 0
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#include <mach/cns3xxx.h>
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--- /dev/null
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+++ b/arch/arm/mach-cns3xxx/include/mach/smp.h
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@@ -0,0 +1,8 @@
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+#ifndef __MACH_SMP_H
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+#define __MACH_SMP_H
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+
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+extern void smp_dma_map_area(const void *, size_t, int);
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+extern void smp_dma_unmap_area(const void *, size_t, int);
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+extern void smp_dma_flush_range(const void *, const void *);
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+
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+#endif
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--- a/arch/arm/mach-cns3xxx/platsmp.c
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+++ b/arch/arm/mach-cns3xxx/platsmp.c
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@@ -24,10 +24,27 @@
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#include <asm/hardware/gic.h>
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#include <asm/smp_scu.h>
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#include <asm/unified.h>
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-
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+#include <asm/fiq.h>
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+#include <mach/smp.h>
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#include <mach/cns3xxx.h>
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+static struct fiq_handler fh = {
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+ .name = "cns3xxx-fiq"
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+};
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+
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+static unsigned int fiq_buffer[8];
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+
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+#define FIQ_ENABLED 0x80000000
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+#define FIQ_GENERATE 0x00010000
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+#define CNS3XXX_MAP_AREA 0x01000000
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+#define CNS3XXX_UNMAP_AREA 0x02000000
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+#define CNS3XXX_FLUSH_RANGE 0x03000000
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+
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extern void cns3xxx_secondary_startup(void);
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+extern unsigned char cns3xxx_fiq_start, cns3xxx_fiq_end;
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+extern unsigned int fiq_number[2];
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+extern struct cpu_cache_fns cpu_cache;
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+struct cpu_cache_fns cpu_cache_save;
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#define SCU_CPU_STATUS 0x08
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static void __iomem *scu_base;
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@@ -38,12 +55,50 @@ static void __iomem *scu_base;
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*/
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volatile int __cpuinitdata pen_release = -1;
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+static void __init cns3xxx_set_fiq_regs(void)
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+{
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+ struct pt_regs FIQ_regs;
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+ unsigned int cpu = smp_processor_id();
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+
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+ if (cpu) {
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+ FIQ_regs.ARM_ip = (unsigned int)&fiq_buffer[4];
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+ FIQ_regs.ARM_sp = (unsigned int)MISC_FIQ_CPU(0);
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+ } else {
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+ FIQ_regs.ARM_ip = (unsigned int)&fiq_buffer[0];
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+ FIQ_regs.ARM_sp = (unsigned int)MISC_FIQ_CPU(1);
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+ }
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+ set_fiq_regs(&FIQ_regs);
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+}
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+
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+static void __init cns3xxx_init_fiq(void)
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+{
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+ void *fiqhandler_start;
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+ unsigned int fiqhandler_length;
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+ int ret;
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+
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+ fiqhandler_start = &cns3xxx_fiq_start;
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+ fiqhandler_length = &cns3xxx_fiq_end - &cns3xxx_fiq_start;
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+
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+ ret = claim_fiq(&fh);
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+
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+ if (ret) {
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+ return;
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+ }
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+
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+ set_fiq_handler(fiqhandler_start, fiqhandler_length);
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+ fiq_buffer[0] = (unsigned int)&fiq_number[0];
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+ fiq_buffer[3] = 0;
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+ fiq_buffer[4] = (unsigned int)&fiq_number[1];
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+ fiq_buffer[7] = 0;
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+}
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+
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+
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/*
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* Write pen_release in a way that is guaranteed to be visible to all
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* observers, irrespective of whether they're taking part in coherency
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* or not. This is necessary for the hotplug code to work reliably.
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*/
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-static void write_pen_release(int val)
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+static void __cpuinit write_pen_release(int val)
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{
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pen_release = val;
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smp_wmb();
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@@ -63,12 +118,25 @@ void __cpuinit platform_secondary_init(u
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gic_secondary_init(0);
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/*
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+ * Setup Secondary Core FIQ regs
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+ */
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+ cns3xxx_set_fiq_regs();
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+
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+ /*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
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write_pen_release(-1);
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/*
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+ * Fixup DMA Operations
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+ *
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+ */
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+ cpu_cache.dma_map_area = (void *)smp_dma_map_area;
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+ cpu_cache.dma_unmap_area = (void *)smp_dma_unmap_area;
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+ cpu_cache.dma_flush_range = (void *)smp_dma_flush_range;
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+
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+ /*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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@@ -171,4 +239,112 @@ void __init platform_smp_prepare_cpus(un
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*/
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__raw_writel(virt_to_phys(cns3xxx_secondary_startup),
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(void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0600));
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+
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+ /*
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+ * Setup FIQ's for main cpu
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+ */
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+ cns3xxx_init_fiq();
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+ cns3xxx_set_fiq_regs();
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+ memcpy((void *)&cpu_cache_save, (void *)&cpu_cache, sizeof(struct cpu_cache_fns));
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+}
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+
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+
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+static inline unsigned long cns3xxx_cpu_id(void)
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+{
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+ unsigned long cpu;
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+
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+ asm volatile(
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+ " mrc p15, 0, %0, c0, c0, 5 @ cns3xxx_cpu_id\n"
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+ : "=r" (cpu) : : "memory", "cc");
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+ return (cpu & 0xf);
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+}
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+
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+void smp_dma_map_area(const void *addr, size_t size, int dir)
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+{
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+ unsigned int cpu;
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+ unsigned long flags;
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+ raw_local_irq_save(flags);
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+ cpu = cns3xxx_cpu_id();
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+ if (cpu) {
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+ fiq_buffer[1] = (unsigned int)addr;
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+ fiq_buffer[2] = size;
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+ fiq_buffer[3] = dir | CNS3XXX_MAP_AREA | FIQ_ENABLED;
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+ smp_mb();
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+ __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
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+
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+ cpu_cache_save.dma_map_area(addr, size, dir);
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+ while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
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+ } else {
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+
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+ fiq_buffer[5] = (unsigned int)addr;
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+ fiq_buffer[6] = size;
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+ fiq_buffer[7] = dir | CNS3XXX_MAP_AREA | FIQ_ENABLED;
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+ smp_mb();
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+ __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
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+
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+ cpu_cache_save.dma_map_area(addr, size, dir);
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+ while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
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+ }
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+ raw_local_irq_restore(flags);
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+}
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+
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+void smp_dma_unmap_area(const void *addr, size_t size, int dir)
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+{
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+ unsigned int cpu;
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+ unsigned long flags;
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+
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+ raw_local_irq_save(flags);
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+ cpu = cns3xxx_cpu_id();
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+ if (cpu) {
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+
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+ fiq_buffer[1] = (unsigned int)addr;
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+ fiq_buffer[2] = size;
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+ fiq_buffer[3] = dir | CNS3XXX_UNMAP_AREA | FIQ_ENABLED;
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+ smp_mb();
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+ __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
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+
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+ cpu_cache_save.dma_unmap_area(addr, size, dir);
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+ while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
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+ } else {
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+
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+ fiq_buffer[5] = (unsigned int)addr;
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+ fiq_buffer[6] = size;
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+ fiq_buffer[7] = dir | CNS3XXX_UNMAP_AREA | FIQ_ENABLED;
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+ smp_mb();
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+ __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
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+
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+ cpu_cache_save.dma_unmap_area(addr, size, dir);
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+ while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
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+ }
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+ raw_local_irq_restore(flags);
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+}
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+
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+void smp_dma_flush_range(const void *start, const void *end)
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+{
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+ unsigned int cpu;
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+ unsigned long flags;
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+ raw_local_irq_save(flags);
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+ cpu = cns3xxx_cpu_id();
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+ if (cpu) {
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+
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+ fiq_buffer[1] = (unsigned int)start;
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+ fiq_buffer[2] = (unsigned int)end;
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+ fiq_buffer[3] = CNS3XXX_FLUSH_RANGE | FIQ_ENABLED;
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+ smp_mb();
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+ __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
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+
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+ cpu_cache_save.dma_flush_range(start, end);
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+ while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
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+ } else {
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+
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+ fiq_buffer[5] = (unsigned int)start;
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+ fiq_buffer[6] = (unsigned int)end;
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+ fiq_buffer[7] = CNS3XXX_FLUSH_RANGE | FIQ_ENABLED;
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+ smp_mb();
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+ __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
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+
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+ cpu_cache_save.dma_flush_range(start, end);
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+ while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
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+ }
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+ raw_local_irq_restore(flags);
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}
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--- a/arch/arm/mm/Kconfig
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+++ b/arch/arm/mm/Kconfig
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@@ -793,7 +793,7 @@ config NEEDS_SYSCALL_FOR_CMPXCHG
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config DMA_CACHE_RWFO
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bool "Enable read/write for ownership DMA cache maintenance"
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- depends on CPU_V6K && SMP
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+ depends on CPU_V6K && SMP && !ARCH_CNS3XXX
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default y
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help
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The Snoop Control Unit on ARM11MPCore does not detect the
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