openwrt/target/linux/ramips/dts/TL-WR840NV5.dts
Serg Studzinskii eb58b14d27 ramips: tl-wr840n-v5: increase firmware partition for 4Mmtk layot
According to console log during TP-Link TL-WR840N v5 OEM firmware update
procedure 0x3e0000-0x3f0000 64kB "config" partition, which is used to store
router's configuration settings, is erased and recreated again during every
OEM firmware update procedure, thus does not contain any valuable factory data.
So it is conviniant to use this extra 64kB erase block for jffs overlay due
limited flash size on this device like it used on TP-Link's ar71xx boards.

Signed-off-by: Serg Studzinskii <serguzhg@gmail.com>
2018-01-18 08:04:18 +01:00

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/dts-v1/;
#include "mt7628an.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
compatible = "tplink,tl-wr840n-v5", "mediatek,mt7628an-soc";
model = "TP-Link TL-WR840N v5";
chosen {
bootargs = "console=ttyS0,115200";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x4000000>;
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <20>;
reset {
label = "reset";
gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
/* LED used is dual-color,dual lead LED */
gpio-leds {
compatible = "gpio-leds";
power {
label = "tl-wr840n-v5:green:power";
gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
};
orange {
label = "tl-wr840n-v5:orange:power";
gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
};
};
};
&spi0 {
status = "okay";
m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
m25p,chunked-io = <32>;
partition@0 {
label = "boot";
reg = <0x0 0x20000>;
read-only;
};
partition@20000 {
label = "firmware";
reg = <0x20000 0x3d0000>;
};
factory: partition@3f0000 {
label = "factory";
reg = <0x3f0000 0x10000>;
read-only;
};
};
};
&ehci {
status = "disabled";
};
&ohci {
status = "disabled";
};
&wmac {
status = "okay";
mtd-mac-address = <&factory 0xf100>;
mediatek,mtd-eeprom = <&factory 0x10000>;
};
&ethernet {
mtd-mac-address = <&factory 0xf100>;
mediatek,portmap = "wllll";
};
&pinctrl {
state_default: pinctrl0 {
gpio {
ralink,group = "p0led_an", "p2led_an", "perst";
ralink,function = "gpio";
};
};
};