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b269a3520d
The default delays RXD 3. RDV 3, TXD 0, TXE 0 doesn't seem to work for some boards. These boards depend on the preset values of u-boot which may differ. This reverts commit f2d4bb96b62512caa161dcc2867c91692fb16a38. Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com> SVN-Revision: 49071
267 lines
7.2 KiB
C
267 lines
7.2 KiB
C
/*
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* TP-LINK Archer C5/C7/TL-WDR4900 v2 board support
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*
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* Copyright (c) 2013 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (c) 2014 施康成 <tenninjas@tenninjas.ca>
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* Copyright (c) 2014 Imre Kaloz <kaloz@openwrt.org>
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*
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* Based on the Qualcomm Atheros AP135/AP136 reference board support code
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* Copyright (c) 2012 Qualcomm Atheros
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <linux/pci.h>
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#include <linux/phy.h>
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#include <linux/gpio.h>
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#include <linux/platform_device.h>
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#include <linux/ath9k_platform.h>
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#include <linux/ar8216_platform.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "common.h"
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#include "dev-ap9x-pci.h"
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#include "dev-eth.h"
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#include "dev-gpio-buttons.h"
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#include "dev-leds-gpio.h"
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#include "dev-m25p80.h"
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#include "dev-spi.h"
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#include "dev-usb.h"
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#include "dev-wmac.h"
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#include "machtypes.h"
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#include "pci.h"
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#define ARCHER_C7_GPIO_LED_WLAN2G 12
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#define ARCHER_C7_GPIO_LED_SYSTEM 14
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#define ARCHER_C7_GPIO_LED_QSS 15
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#define ARCHER_C7_GPIO_LED_WLAN5G 17
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#define ARCHER_C7_GPIO_LED_USB1 18
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#define ARCHER_C7_GPIO_LED_USB2 19
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#define ARCHER_C7_GPIO_BTN_RFKILL 13
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#define ARCHER_C7_GPIO_BTN_RESET 16
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#define ARCHER_C7_GPIO_USB1_POWER 22
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#define ARCHER_C7_GPIO_USB2_POWER 21
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#define ARCHER_C7_KEYS_POLL_INTERVAL 20 /* msecs */
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#define ARCHER_C7_KEYS_DEBOUNCE_INTERVAL (3 * ARCHER_C7_KEYS_POLL_INTERVAL)
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#define ARCHER_C7_WMAC_CALDATA_OFFSET 0x1000
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#define ARCHER_C7_PCIE_CALDATA_OFFSET 0x5000
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static const char *archer_c7_part_probes[] = {
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"tp-link",
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NULL,
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};
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static struct flash_platform_data archer_c7_flash_data = {
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.part_probes = archer_c7_part_probes,
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};
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static struct gpio_led archer_c7_leds_gpio[] __initdata = {
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{
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.name = "tp-link:blue:qss",
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.gpio = ARCHER_C7_GPIO_LED_QSS,
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.active_low = 1,
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},
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{
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.name = "tp-link:blue:system",
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.gpio = ARCHER_C7_GPIO_LED_SYSTEM,
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.active_low = 1,
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},
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{
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.name = "tp-link:blue:wlan2g",
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.gpio = ARCHER_C7_GPIO_LED_WLAN2G,
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.active_low = 1,
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},
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{
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.name = "tp-link:blue:wlan5g",
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.gpio = ARCHER_C7_GPIO_LED_WLAN5G,
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.active_low = 1,
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},
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{
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.name = "tp-link:green:usb1",
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.gpio = ARCHER_C7_GPIO_LED_USB1,
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.active_low = 1,
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},
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{
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.name = "tp-link:green:usb2",
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.gpio = ARCHER_C7_GPIO_LED_USB2,
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.active_low = 1,
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},
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};
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static struct gpio_keys_button archer_c7_gpio_keys[] __initdata = {
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{
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.desc = "Reset button",
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.type = EV_KEY,
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.code = KEY_WPS_BUTTON,
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.debounce_interval = ARCHER_C7_KEYS_DEBOUNCE_INTERVAL,
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.gpio = ARCHER_C7_GPIO_BTN_RESET,
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.active_low = 1,
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},
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{
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.desc = "RFKILL switch",
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.type = EV_SW,
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.code = KEY_RFKILL,
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.debounce_interval = ARCHER_C7_KEYS_DEBOUNCE_INTERVAL,
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.gpio = ARCHER_C7_GPIO_BTN_RFKILL,
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},
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};
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static const struct ar8327_led_info archer_c7_leds_ar8327[] __initconst = {
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AR8327_LED_INFO(PHY0_0, HW, "tp-link:blue:wan"),
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AR8327_LED_INFO(PHY1_0, HW, "tp-link:blue:lan1"),
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AR8327_LED_INFO(PHY2_0, HW, "tp-link:blue:lan2"),
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AR8327_LED_INFO(PHY3_0, HW, "tp-link:blue:lan3"),
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AR8327_LED_INFO(PHY4_0, HW, "tp-link:blue:lan4"),
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};
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/* GMAC0 of the AR8327 switch is connected to the QCA9558 SoC via SGMII */
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static struct ar8327_pad_cfg archer_c7_ar8327_pad0_cfg = {
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.mode = AR8327_PAD_MAC_SGMII,
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.sgmii_delay_en = true,
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};
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/* GMAC6 of the AR8327 switch is connected to the QCA9558 SoC via RGMII */
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static struct ar8327_pad_cfg archer_c7_ar8327_pad6_cfg = {
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.mode = AR8327_PAD_MAC_RGMII,
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.txclk_delay_en = true,
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.rxclk_delay_en = true,
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.txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
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.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
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};
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static struct ar8327_led_cfg archer_c7_ar8327_led_cfg = {
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.led_ctrl0 = 0xc737c737,
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.led_ctrl1 = 0x00000000,
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.led_ctrl2 = 0x00000000,
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.led_ctrl3 = 0x0030c300,
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.open_drain = false,
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};
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static struct ar8327_platform_data archer_c7_ar8327_data = {
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.pad0_cfg = &archer_c7_ar8327_pad0_cfg,
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.pad6_cfg = &archer_c7_ar8327_pad6_cfg,
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.port0_cfg = {
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.force_link = 1,
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.speed = AR8327_PORT_SPEED_1000,
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.duplex = 1,
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.txpause = 1,
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.rxpause = 1,
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},
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.port6_cfg = {
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.force_link = 1,
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.speed = AR8327_PORT_SPEED_1000,
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.duplex = 1,
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.txpause = 1,
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.rxpause = 1,
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},
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.led_cfg = &archer_c7_ar8327_led_cfg,
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.num_leds = ARRAY_SIZE(archer_c7_leds_ar8327),
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.leds = archer_c7_leds_ar8327,
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};
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static struct mdio_board_info archer_c7_mdio0_info[] = {
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{
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.bus_id = "ag71xx-mdio.0",
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.phy_addr = 0,
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.platform_data = &archer_c7_ar8327_data,
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},
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};
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static void __init common_setup(bool pcie_slot)
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{
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u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
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u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
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u8 tmpmac[ETH_ALEN];
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ath79_register_m25p80(&archer_c7_flash_data);
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ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c7_leds_gpio),
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archer_c7_leds_gpio);
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ath79_register_gpio_keys_polled(-1, ARCHER_C7_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(archer_c7_gpio_keys),
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archer_c7_gpio_keys);
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ath79_init_mac(tmpmac, mac, -1);
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ath79_register_wmac(art + ARCHER_C7_WMAC_CALDATA_OFFSET, tmpmac);
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if (pcie_slot) {
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ath79_register_pci();
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} else {
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ath79_init_mac(tmpmac, mac, -1);
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ap9x_pci_setup_wmac_led_pin(0, 0);
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ap91_pci_init(art + ARCHER_C7_PCIE_CALDATA_OFFSET, tmpmac);
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}
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mdiobus_register_board_info(archer_c7_mdio0_info,
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ARRAY_SIZE(archer_c7_mdio0_info));
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ath79_register_mdio(0, 0x0);
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
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/* GMAC0 is connected to the RMGII interface */
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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ath79_eth0_data.phy_mask = BIT(0);
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ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
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ath79_eth0_pll_data.pll_1000 = 0x56000000;
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ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
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ath79_register_eth(0);
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/* GMAC1 is connected to the SGMII interface */
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ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
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ath79_eth1_data.speed = SPEED_1000;
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ath79_eth1_data.duplex = DUPLEX_FULL;
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ath79_eth1_pll_data.pll_1000 = 0x03000101;
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ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
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ath79_register_eth(1);
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gpio_request_one(ARCHER_C7_GPIO_USB1_POWER,
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GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
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"USB1 power");
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gpio_request_one(ARCHER_C7_GPIO_USB2_POWER,
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GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
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"USB2 power");
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ath79_register_usb();
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}
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static void __init archer_c5_setup(void)
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{
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common_setup(true);
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}
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MIPS_MACHINE(ATH79_MACH_ARCHER_C5, "ARCHER-C5", "TP-LINK Archer C5",
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archer_c5_setup);
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static void __init archer_c7_setup(void)
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{
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common_setup(true);
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}
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MIPS_MACHINE(ATH79_MACH_ARCHER_C7, "ARCHER-C7", "TP-LINK Archer C7",
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archer_c7_setup);
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static void __init tl_wdr4900_v2_setup(void)
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{
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common_setup(false);
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}
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MIPS_MACHINE(ATH79_MACH_TL_WDR4900_V2, "TL-WDR4900-v2", "TP-LINK TL-WDR4900 v2",
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tl_wdr4900_v2_setup)
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