mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-22 23:12:32 +00:00
5ecc0cfd6f
Changelog since 5.4.24 mentions CVE-2019-19769, CVE-2020-8648, CVE-2020-8649 and CVE-2020-8647. Removed upstreamed: generic: 507-v5.6-iio-chemical-sps30-fix-missing-triggered-buffer-depe.patch generic: 600-ipv6-addrconf-call-ipv6_mc_up-for-non-Ethernet-inter.patch bcm27xx: 950-0435-ASoC-pcm512x-Fix-unbalanced-regulator-enable-call-in.patch ipq806x: 701-stmmac-fix-notifier-registration.patch lantiq: 002-pinctrl-falcon-fix-syntax-error.patch octeontx: 0002-net-thunderx-workaround-BGX-TX-Underflow-issue.patch Run tested: apu2, qemu-x86-64, apalis, a64-olinuxino, nbg6617 Build tested: sunxi/a53, imx6, x86/64, ipq40xx Tested-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk> [apu2] Signed-off-by: Petr Štetiar <ynezz@true.cz>
552 lines
13 KiB
Diff
552 lines
13 KiB
Diff
From 9a820b55817011f53771e6bfebae5fe059f0a534 Mon Sep 17 00:00:00 2001
|
|
From: Robert Jones <rjones@gateworks.com>
|
|
Date: Wed, 8 Jan 2020 07:44:24 -0800
|
|
Subject: [PATCH 4/4] ARM: dts: imx: Add GW5912 board support
|
|
|
|
The Gateworks GW5912 is an IMX6 SoC based single board computer with:
|
|
- IMX6Q or IMX6DL
|
|
- 32bit DDR3 DRAM
|
|
- GbE RJ45 front-panel
|
|
- 4x miniPCIe socket with PCI Gen2, USB2
|
|
- 1x miniPCIe socket with PCI Gen2, USB2, mSATA
|
|
- 1x miniPCIe socket with PCI Gen2, USB2, mezzanine
|
|
- 10V to 60V DC input barrel jack
|
|
- 3axis accelerometer (lis2de12)
|
|
- GPS (ublox ZOE-M8Q)
|
|
- bi-color front-panel LED
|
|
- 256MB NAND boot device
|
|
- nanoSIM/microSD socket (with UHS-I support)
|
|
- user pushbutton
|
|
- Gateworks System Controller (hwmon, pushbutton controller, EEPROM)
|
|
- CAN Bus transceiver (mcp2562)
|
|
- RS232 transceiver (1x UART with flow-control or 2x UART (build option)
|
|
- off-board SPI connector (1x chip-select)
|
|
|
|
Signed-off-by: Robert Jones <rjones@gateworks.com>
|
|
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
|
|
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
---
|
|
arch/arm/boot/dts/Makefile | 2 +
|
|
arch/arm/boot/dts/imx6dl-gw5912.dts | 13 +
|
|
arch/arm/boot/dts/imx6q-gw5912.dts | 13 +
|
|
arch/arm/boot/dts/imx6qdl-gw5912.dtsi | 461 ++++++++++++++++++++++++++++++++++
|
|
4 files changed, 489 insertions(+)
|
|
create mode 100644 arch/arm/boot/dts/imx6dl-gw5912.dts
|
|
create mode 100644 arch/arm/boot/dts/imx6q-gw5912.dts
|
|
create mode 100644 arch/arm/boot/dts/imx6qdl-gw5912.dtsi
|
|
|
|
--- a/arch/arm/boot/dts/Makefile
|
|
+++ b/arch/arm/boot/dts/Makefile
|
|
@@ -420,6 +420,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
|
|
imx6dl-gw5904.dtb \
|
|
imx6dl-gw5907.dtb \
|
|
imx6dl-gw5910.dtb \
|
|
+ imx6dl-gw5912.dtb \
|
|
imx6dl-gw5913.dtb \
|
|
imx6dl-hummingboard.dtb \
|
|
imx6dl-hummingboard-emmc-som-v15.dtb \
|
|
@@ -494,6 +495,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
|
|
imx6q-gw5904.dtb \
|
|
imx6q-gw5907.dtb \
|
|
imx6q-gw5910.dtb \
|
|
+ imx6q-gw5912.dtb \
|
|
imx6q-gw5913.dtb \
|
|
imx6q-h100.dtb \
|
|
imx6q-hummingboard.dtb \
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/imx6dl-gw5912.dts
|
|
@@ -0,0 +1,13 @@
|
|
+// SPDX-License-Identifier: GPL-2.0
|
|
+/*
|
|
+ * Copyright 2019 Gateworks Corporation
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+#include "imx6dl.dtsi"
|
|
+#include "imx6qdl-gw5912.dtsi"
|
|
+
|
|
+/ {
|
|
+ model = "Gateworks Ventana i.MX6 DualLite/Solo GW5912";
|
|
+ compatible = "gw,imx6dl-gw5912", "gw,ventana", "fsl,imx6dl";
|
|
+};
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/imx6q-gw5912.dts
|
|
@@ -0,0 +1,13 @@
|
|
+// SPDX-License-Identifier: GPL-2.0
|
|
+/*
|
|
+ * Copyright 2019 Gateworks Corporation
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+#include "imx6q.dtsi"
|
|
+#include "imx6qdl-gw5912.dtsi"
|
|
+
|
|
+/ {
|
|
+ model = "Gateworks Ventana i.MX6 Dual/Quad GW5912";
|
|
+ compatible = "gw,imx6q-gw5912", "gw,ventana", "fsl,imx6q";
|
|
+};
|
|
--- /dev/null
|
|
+++ b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi
|
|
@@ -0,0 +1,461 @@
|
|
+// SPDX-License-Identifier: GPL-2.0
|
|
+/*
|
|
+ * Copyright 2019 Gateworks Corporation
|
|
+ */
|
|
+
|
|
+#include <dt-bindings/gpio/gpio.h>
|
|
+
|
|
+/ {
|
|
+ /* these are used by bootloader for disabling nodes */
|
|
+ aliases {
|
|
+ led0 = &led0;
|
|
+ led1 = &led1;
|
|
+ led2 = &led2;
|
|
+ nand = &gpmi;
|
|
+ usb0 = &usbh1;
|
|
+ usb1 = &usbotg;
|
|
+ };
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = &uart2;
|
|
+ };
|
|
+
|
|
+ leds {
|
|
+ compatible = "gpio-leds";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_gpio_leds>;
|
|
+
|
|
+ led0: user1 {
|
|
+ label = "user1";
|
|
+ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
|
|
+ default-state = "on";
|
|
+ linux,default-trigger = "heartbeat";
|
|
+ };
|
|
+
|
|
+ led1: user2 {
|
|
+ label = "user2";
|
|
+ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
|
|
+ default-state = "off";
|
|
+ };
|
|
+
|
|
+ led2: user3 {
|
|
+ label = "user3";
|
|
+ gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
|
|
+ default-state = "off";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ memory@10000000 {
|
|
+ device_type = "memory";
|
|
+ reg = <0x10000000 0x40000000>;
|
|
+ };
|
|
+
|
|
+ pps {
|
|
+ compatible = "pps-gpio";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_pps>;
|
|
+ gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
|
|
+ };
|
|
+
|
|
+ reg_3p3v: regulator-3p3v {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "3P3V";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+
|
|
+ reg_usb_vbus: regulator-5p0v {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "usb_vbus";
|
|
+ regulator-min-microvolt = <5000000>;
|
|
+ regulator-max-microvolt = <5000000>;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+};
|
|
+
|
|
+&can1 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_flexcan1>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&ecspi2 {
|
|
+ cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_ecspi2>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&fec {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_enet>;
|
|
+ phy-mode = "rgmii-id";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&gpmi {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&i2c1 {
|
|
+ clock-frequency = <100000>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_i2c1>;
|
|
+ status = "okay";
|
|
+
|
|
+ gpio@23 {
|
|
+ compatible = "nxp,pca9555";
|
|
+ reg = <0x23>;
|
|
+ gpio-controller;
|
|
+ #gpio-cells = <2>;
|
|
+ };
|
|
+
|
|
+ eeprom@50 {
|
|
+ compatible = "atmel,24c02";
|
|
+ reg = <0x50>;
|
|
+ pagesize = <16>;
|
|
+ };
|
|
+
|
|
+ eeprom@51 {
|
|
+ compatible = "atmel,24c02";
|
|
+ reg = <0x51>;
|
|
+ pagesize = <16>;
|
|
+ };
|
|
+
|
|
+ eeprom@52 {
|
|
+ compatible = "atmel,24c02";
|
|
+ reg = <0x52>;
|
|
+ pagesize = <16>;
|
|
+ };
|
|
+
|
|
+ eeprom@53 {
|
|
+ compatible = "atmel,24c02";
|
|
+ reg = <0x53>;
|
|
+ pagesize = <16>;
|
|
+ };
|
|
+
|
|
+ rtc@68 {
|
|
+ compatible = "dallas,ds1672";
|
|
+ reg = <0x68>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c2 {
|
|
+ clock-frequency = <100000>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_i2c2>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&i2c3 {
|
|
+ clock-frequency = <100000>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_i2c3>;
|
|
+ status = "okay";
|
|
+
|
|
+ accel@19 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_accel>;
|
|
+ compatible = "st,lis2de12";
|
|
+ reg = <0x19>;
|
|
+ st,drdy-int-pin = <1>;
|
|
+ interrupt-parent = <&gpio7>;
|
|
+ interrupts = <13 0>;
|
|
+ interrupt-names = "INT1";
|
|
+ };
|
|
+};
|
|
+
|
|
+&pcie {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_pcie>;
|
|
+ reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&pwm1 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&pwm2 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&pwm3 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&pwm4 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&uart1 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_uart1>;
|
|
+ rts-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart2 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_uart2>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart5 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_uart5>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbotg {
|
|
+ vbus-supply = <®_usb_vbus>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_usbotg>;
|
|
+ disable-over-current;
|
|
+ dr_mode = "host";
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usbh1 {
|
|
+ vbus-supply = <®_usb_vbus>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usdhc3 {
|
|
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
+ pinctrl-0 = <&pinctrl_usdhc3>;
|
|
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
|
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
|
+ cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
|
|
+ vmmc-supply = <®_3p3v>;
|
|
+ no-1-8-v; /* firmware will remove if board revision supports */
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&wdog1 {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&wdog2 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pinctrl_wdog>;
|
|
+ fsl,ext-reset-output;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&iomuxc {
|
|
+ pinctrl_accel: accelmuxgrp {
|
|
+ fsl,pins = <
|
|
+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_enet: enetgrp {
|
|
+ fsl,pins = <
|
|
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
|
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
|
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
|
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
|
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
|
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
|
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
|
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
|
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
|
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
|
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
|
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
|
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
|
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
|
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_ecspi2: escpi2grp {
|
|
+ fsl,pins = <
|
|
+ MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
|
|
+ MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
|
|
+ MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
|
|
+ MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_flexcan1: flexcan1grp {
|
|
+ fsl,pins = <
|
|
+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
|
|
+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
|
|
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_gpio_leds: gpioledsgrp {
|
|
+ fsl,pins = <
|
|
+ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
|
|
+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
|
|
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_gpmi_nand: gpminandgrp {
|
|
+ fsl,pins = <
|
|
+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
|
|
+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
|
|
+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
|
|
+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
|
|
+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
|
|
+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
|
|
+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
|
|
+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
|
|
+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
|
|
+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
|
|
+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
|
|
+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
|
|
+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
|
|
+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
|
|
+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_i2c1: i2c1grp {
|
|
+ fsl,pins = <
|
|
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
|
|
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
|
|
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_i2c2: i2c2grp {
|
|
+ fsl,pins = <
|
|
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
|
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_i2c3: i2c3grp {
|
|
+ fsl,pins = <
|
|
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
|
|
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_pcie: pciegrp {
|
|
+ fsl,pins = <
|
|
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
|
|
+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_pps: ppsgrp {
|
|
+ fsl,pins = <
|
|
+ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_pwm1: pwm1grp {
|
|
+ fsl,pins = <
|
|
+ MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_pwm2: pwm2grp {
|
|
+ fsl,pins = <
|
|
+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_pwm3: pwm3grp {
|
|
+ fsl,pins = <
|
|
+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_pwm4: pwm4grp {
|
|
+ fsl,pins = <
|
|
+ MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_uart1: uart1grp {
|
|
+ fsl,pins = <
|
|
+ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
|
|
+ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
|
|
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b1
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_uart2: uart2grp {
|
|
+ fsl,pins = <
|
|
+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
|
|
+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
|
|
+ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b1
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_uart5: uart5grp {
|
|
+ fsl,pins = <
|
|
+ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
|
|
+ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_usbotg: usbotggrp {
|
|
+ fsl,pins = <
|
|
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_usdhc3: usdhc3grp {
|
|
+ fsl,pins = <
|
|
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
|
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
|
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
|
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
|
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
|
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
|
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
|
|
+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
|
|
+ fsl,pins = <
|
|
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
|
|
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
|
|
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
|
|
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
|
|
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
|
|
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
|
|
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
|
|
+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
|
|
+ fsl,pins = <
|
|
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
|
|
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
|
|
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
|
|
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
|
|
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
|
|
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
|
|
+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
|
|
+ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
|
|
+ >;
|
|
+ };
|
|
+
|
|
+ pinctrl_wdog: wdoggrp {
|
|
+ fsl,pins = <
|
|
+ MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0
|
|
+ >;
|
|
+ };
|
|
+};
|