mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-22 23:12:32 +00:00
ab47e21472
phy-mode is already set to rgmii for eth0 and sgmii for eth1 in qca955x.dtsi, no need to do that again in the device DTS files. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
169 lines
2.6 KiB
Plaintext
169 lines
2.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
|
|
|
#include "qca955x.dtsi"
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/input/input.h>
|
|
|
|
/ {
|
|
compatible = "dlink,dap-2695-a1", "qca,qca9558";
|
|
model = "D-link DAP-2695-A1";
|
|
|
|
aliases {
|
|
led-boot = &led_power_red;
|
|
led-failsafe = &led_power_red;
|
|
led-running = &led_power_green;
|
|
led-upgrade = &led_power_red;
|
|
};
|
|
|
|
leds {
|
|
compatible = "gpio-leds";
|
|
|
|
led_power_green: power_green {
|
|
label = "green:power";
|
|
gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
|
|
default-state = "on";
|
|
};
|
|
|
|
led_power_red: power_red {
|
|
label = "red:power";
|
|
gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
wifi2g {
|
|
label = "green:wifi2g";
|
|
gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
|
|
linux,default-trigger = "phy1tpt";
|
|
};
|
|
};
|
|
|
|
keys {
|
|
compatible = "gpio-keys";
|
|
|
|
reset {
|
|
label = "reset";
|
|
linux,code = <KEY_RESTART>;
|
|
gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&spi {
|
|
status = "okay";
|
|
|
|
flash@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "mx25l12805d";
|
|
reg = <0>;
|
|
spi-max-frequency = <25000000>;
|
|
|
|
partitions {
|
|
compatible = "fixed-partitions";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
partition@0 {
|
|
label = "u-boot";
|
|
reg = <0x000000 0x040000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@40000 {
|
|
label = "bdcfg";
|
|
reg = <0x040000 0x010000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@50000 {
|
|
label = "rgdb";
|
|
reg = <0x050000 0x010000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@60000 {
|
|
label = "langpack";
|
|
reg = <0x060000 0x010000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@70000 {
|
|
compatible = "wrg";
|
|
label = "firmware";
|
|
reg = <0x070000 0xf00000>;
|
|
};
|
|
|
|
partition@f70000 {
|
|
label = "captival";
|
|
reg = <0xf70000 0x070000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@fe0000 {
|
|
label = "certificate";
|
|
reg = <0xfe0000 0x010000>;
|
|
read-only;
|
|
};
|
|
|
|
art: partition@ff0000 {
|
|
label = "art";
|
|
reg = <0xff0000 0x010000>;
|
|
read-only;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&mdio0 {
|
|
status = "okay";
|
|
|
|
phy0: ethernet-phy@0 {
|
|
reg = <0>;
|
|
|
|
qca,ar8327-initvals = <
|
|
0x04 0x07600000 /* PORT0_PAD_CTRL */
|
|
0x0c 0x00080080 /* PORT6_PAD_CTRL */
|
|
0x7c 0x0000007e /* PORT0_STATUS */
|
|
0x94 0x0000007e /* PORT6_STATUS */
|
|
>;
|
|
};
|
|
};
|
|
|
|
ð0 {
|
|
status = "okay";
|
|
|
|
phy-handle = <&phy0>;
|
|
pll-data = <0x56000000 0x00000101 0x00001616>;
|
|
|
|
fixed-link {
|
|
speed = <1000>;
|
|
full-duplex;
|
|
};
|
|
};
|
|
|
|
ð1 {
|
|
status = "okay";
|
|
|
|
phy-mask = <0>;
|
|
pll-data = <0x03000101 0x00000101 0x00001616>;
|
|
|
|
fixed-link {
|
|
speed = <1000>;
|
|
full-duplex;
|
|
};
|
|
};
|
|
|
|
&pcie0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&uart {
|
|
status = "okay";
|
|
};
|
|
|
|
&wmac {
|
|
status = "okay";
|
|
|
|
qca,no-eeprom;
|
|
};
|