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Over a year ago in a commit ac96a1665a ("bcm53xx: update Disable MMU
and Dcache during decompression") we switched to Florian's patch for
workarounding CFE bug. The main difference was using a part of existing
__armv7_mmu_cache_flush instead of implementing flushing separately.
This worked well for Northstar devices but doesn't work for BCM53573 as
these devices simply don't start booting with Florian's patch. It's
because of the ldmfd ASM instruction in the __armv7_mmu_cache_flush.
So this commit switches back to using standalone implementation. This
time instead of copying Broadcom's copy of cache-v7.S, we just make a
copy of the original file on our own. Unfortunately we can't cross-dir
compile cache-v7.S from ../../mm/ as that one also adds __INITDATA with
define_cache_functions v7 which would just trigger
> Error: unrecognized/unsupported machine ID (r1 = 0x0000007f).
The only real change Broadcom did in copied .S file was modifying mcr
instruction to use c6 instead of c14. It isn't clear to me if we really
need it, but let's use it for now.
By the way we also update commit message of the
[PATCH] ARM: BCM5301X: Disable MMU and Dcache during decompression
This makes kernel booting on BCM53573 successfully.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
101 lines
2.9 KiB
Diff
101 lines
2.9 KiB
Diff
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
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Date: Wed, 24 Sep 2014 22:14:07 +0200
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Subject: [PATCH] ARM: BCM5301X: Disable MMU and Dcache during decompression
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Broadcom devices have broken CFE (bootloader) that leaves hardware in an
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invalid state. It causes problems with booting Linux. On Northstar
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devices kernel was randomly hanging in ~25% of tries during early init.
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Hangs used to happen at random places in the start_kernel. On BCM53573
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kernel doesn't even seem to start booting.
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To workaround this problem we need to do following very early:
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1) Clear 2 following bits in the SCTLR register:
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#define CR_M (1 << 0) /* MMU enable */
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#define CR_C (1 << 2) /* Dcache enable */
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2) Flush the whole D-cache
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3) Disable L2 cache
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Unfortunately this patch is not upstreamable as it does above things
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unconditionally. We can't check if we are running on Broadcom platform
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in any safe way and doing such hacks with ARCH_MULTI_V7 is unacceptable
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as it could break other devices support.
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Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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---
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--- a/arch/arm/boot/compressed/Makefile
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+++ b/arch/arm/boot/compressed/Makefile
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@@ -31,6 +31,11 @@ ifeq ($(CONFIG_ARCH_ACORN),y)
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OBJS += ll_char_wr.o font.o
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endif
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+ifeq ($(CONFIG_ARCH_BCM_5301X),y)
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+OBJS += head-bcm_5301x-mpcore.o
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+OBJS += cache-v7-min.o
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+endif
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+
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ifeq ($(CONFIG_ARCH_SA1100),y)
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OBJS += head-sa1100.o
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endif
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--- /dev/null
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+++ b/arch/arm/boot/compressed/head-bcm_5301x-mpcore.S
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@@ -0,0 +1,37 @@
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+/*
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+ *
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+ * Platform specific tweaks. This is merged into head.S by the linker.
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+ *
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+ */
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+
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+#include <linux/linkage.h>
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+#include <asm/assembler.h>
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+#include <asm/cp15.h>
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+
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+ .section ".start", "ax"
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+
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+/*
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+ * This code section is spliced into the head code by the linker
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+ */
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+
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+__plat_uncompress_start:
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+
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+ @ Preserve r8/r7 i.e. kernel entry values
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+ mov r12, r8
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+
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+ @ Clear MMU enable and Dcache enable bits
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+ mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR
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+ bic r0, #CR_C|CR_M
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+ mcr p15, 0, r0, c1, c0, 0 @ Write SCTLR
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+ nop
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+
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+ @ Call the cache invalidation routine
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+ bl v7_flush_dcache_all
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+ nop
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+ mov r0,#0
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+ ldr r3, =0x19022000 @ L2 cache controller, control reg
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+ str r0, [r3, #0x100] @ Disable L2 cache
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+ nop
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+
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+ @ Restore
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+ mov r8, r12
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--- a/arch/arm/boot/compressed/cache-v7-min.S
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+++ b/arch/arm/boot/compressed/cache-v7-min.S
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@@ -51,7 +51,7 @@ loop2:
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loop3:
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orr r11, r10, r9, lsl r5 @ factor way and cache number into r11
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orr r11, r11, r7, lsl r2 @ factor index number into r11
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- mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
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+ mcr p15, 0, r11, c7, c6, 2 @ Invalidate line
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subs r9, r9, #1 @ decrement the way
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bge loop3
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subs r7, r7, #1 @ decrement the index
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@@ -63,5 +63,6 @@ skip:
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finished:
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mov r10, #0 @ swith back to cache level 0
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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+ dsb
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isb
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mov pc, lr
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