mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-20 22:23:27 +00:00
39 lines
1.6 KiB
Diff
39 lines
1.6 KiB
Diff
From 2cd0c0202f138fa95b3fbb027e87b191ad0b1884 Mon Sep 17 00:00:00 2001
|
|
From: Florian Fainelli <f.fainelli@gmail.com>
|
|
Date: Tue, 24 May 2016 11:41:58 -0700
|
|
Subject: [PATCH 2/3] ARM: dts: BCM5301X: Add SRAB interrupts
|
|
|
|
Add interrupt mapping for the Switch Register Access Block. Only 12
|
|
interrupts are usable at the moment even though up to 32 are dedicated
|
|
to the SRAB.
|
|
|
|
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
|
|
---
|
|
arch/arm/boot/dts/bcm5301x.dtsi | 15 +++++++++++++++
|
|
1 file changed, 15 insertions(+)
|
|
|
|
--- a/arch/arm/boot/dts/bcm5301x.dtsi
|
|
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
|
|
@@ -153,6 +153,21 @@
|
|
/* ChipCommon */
|
|
<0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
+ /* Switch Register Access Block */
|
|
+ <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
|
+
|
|
/* PCIe Controller 0 */
|
|
<0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
|