mirror of
https://github.com/openwrt/openwrt.git
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120 lines
2.2 KiB
Diff
120 lines
2.2 KiB
Diff
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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@@ -1,7 +1,6 @@
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/*
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- * Copyright (c) 2017 MediaTek Inc.
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- * Author: Ming Huang <ming.huang@mediatek.com>
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- * Sean Wang <sean.wang@mediatek.com>
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+ * Copyright (c) 2018 MediaTek Inc.
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+ * Author: Ryder Lee <ryder.lee@mediatek.com>
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*
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* SPDX-License-Identifier: (GPL-2.0 OR MIT)
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*/
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@@ -23,7 +22,7 @@
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chosen {
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stdout-path = "serial0:115200n8";
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- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
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+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
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};
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cpus {
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@@ -40,23 +39,22 @@
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gpio-keys {
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compatible = "gpio-keys";
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- poll-interval = <100>;
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factory {
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label = "factory";
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linux,code = <BTN_0>;
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- gpios = <&pio 0 0>;
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+ gpios = <&pio 0 GPIO_ACTIVE_LOW>;
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};
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wps {
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label = "wps";
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linux,code = <KEY_WPS_BUTTON>;
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- gpios = <&pio 102 0>;
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+ gpios = <&pio 102 GPIO_ACTIVE_LOW>;
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};
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};
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memory {
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- reg = <0 0x40000000 0 0x20000000>;
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+ reg = <0 0x40000000 0 0x40000000>;
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};
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reg_1p8v: regulator-1p8v {
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@@ -132,22 +130,22 @@
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port@0 {
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reg = <0>;
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- label = "lan0";
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+ label = "lan1";
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};
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port@1 {
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reg = <1>;
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- label = "lan1";
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+ label = "lan2";
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};
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port@2 {
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reg = <2>;
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- label = "lan2";
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+ label = "lan3";
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};
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port@3 {
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reg = <3>;
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- label = "lan3";
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+ label = "lan4";
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};
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port@4 {
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@@ -236,15 +234,28 @@
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&pcie {
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pinctrl-names = "default";
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- pinctrl-0 = <&pcie0_pins>;
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+ pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
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status = "okay";
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pcie@0,0 {
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status = "okay";
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};
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+
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+ pcie@1,0 {
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+ status = "okay";
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+ };
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};
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&pio {
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+ /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
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+ * SATA functions. i.e. output-high: PCIe, output-low: SATA
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+ */
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+ asm_sel {
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+ gpio-hog;
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+ gpios = <90 GPIO_ACTIVE_HIGH>;
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+ output-high;
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+ };
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+
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/* eMMC is shared pin with parallel NAND */
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emmc_pins_default: emmc-pins-default {
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mux {
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@@ -521,11 +532,11 @@
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};
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&sata {
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- status = "okay";
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+ status = "disabled";
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};
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&sata_phy {
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- status = "okay";
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+ status = "disabled";
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};
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&spi0 {
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