mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-20 14:13:16 +00:00
c6aac196b8
The pinctrl initialization fails with the MSM pinctrl code and gpio-hogs because either the gpio ranges are not yet initialized (missing gpio-range in DT) or that the msm driver unconditionally tries to re-initializes the ranges (gpio-range in DT). To allow gpio-hogs and similar early-boot gpio code, the gpio-ranges must be in the device tree and the pinctrl-msm code must check whether the range was already initialized by the DT. Signed-off-by: Sven Eckelmann <sven.eckelmann@openmesh.com> [drop changes to unrelated dtsi files, refresh patches] Signed-off-by: Mathias Kresin <dev@kresin.me>
110 lines
3.3 KiB
Diff
110 lines
3.3 KiB
Diff
From 6a6c067b7ce2b3de4efbafddc134afbea3ddc1a3 Mon Sep 17 00:00:00 2001
|
|
From: Matthew McClintock <mmcclint@codeaurora.org>
|
|
Date: Fri, 8 Apr 2016 15:26:10 -0500
|
|
Subject: [PATCH] qcom: ipq4019: use v2 of the kpss bringup mechanism
|
|
|
|
v1 was the incorrect choice here and sometimes the board
|
|
would not come up properly.
|
|
|
|
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
|
|
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
|
---
|
|
Changes:
|
|
- moved L2-Cache to be a subnode of cpu0
|
|
---
|
|
arch/arm/boot/dts/qcom-ipq4019.dtsi | 32 ++++++++++++++++++++++++--------
|
|
1 file changed, 24 insertions(+), 8 deletions(-)
|
|
|
|
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
|
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
|
@@ -36,19 +36,27 @@
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
- enable-method = "qcom,kpss-acc-v1";
|
|
+ enable-method = "qcom,kpss-acc-v2";
|
|
+ next-level-cache = <&L2>;
|
|
qcom,acc = <&acc0>;
|
|
qcom,saw = <&saw0>;
|
|
reg = <0x0>;
|
|
clocks = <&gcc GCC_APPS_CLK_SRC>;
|
|
clock-frequency = <0>;
|
|
operating-points-v2 = <&cpu0_opp_table>;
|
|
+
|
|
+ L2: l2-cache {
|
|
+ compatible = "qcom,arch-cache";
|
|
+ cache-level = <2>;
|
|
+ qcom,saw = <&saw_l2>;
|
|
+ };
|
|
};
|
|
|
|
cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
- enable-method = "qcom,kpss-acc-v1";
|
|
+ enable-method = "qcom,kpss-acc-v2";
|
|
+ next-level-cache = <&L2>;
|
|
qcom,acc = <&acc1>;
|
|
qcom,saw = <&saw1>;
|
|
reg = <0x1>;
|
|
@@ -60,7 +68,8 @@
|
|
cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
- enable-method = "qcom,kpss-acc-v1";
|
|
+ enable-method = "qcom,kpss-acc-v2";
|
|
+ next-level-cache = <&L2>;
|
|
qcom,acc = <&acc2>;
|
|
qcom,saw = <&saw2>;
|
|
reg = <0x2>;
|
|
@@ -72,7 +81,8 @@
|
|
cpu@3 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a7";
|
|
- enable-method = "qcom,kpss-acc-v1";
|
|
+ enable-method = "qcom,kpss-acc-v2";
|
|
+ next-level-cache = <&L2>;
|
|
qcom,acc = <&acc3>;
|
|
qcom,saw = <&saw3>;
|
|
reg = <0x3>;
|
|
@@ -265,22 +275,22 @@
|
|
};
|
|
|
|
acc0: clock-controller@b088000 {
|
|
- compatible = "qcom,kpss-acc-v1";
|
|
+ compatible = "qcom,kpss-acc-v2";
|
|
reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
|
|
};
|
|
|
|
acc1: clock-controller@b098000 {
|
|
- compatible = "qcom,kpss-acc-v1";
|
|
+ compatible = "qcom,kpss-acc-v2";
|
|
reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
|
|
};
|
|
|
|
acc2: clock-controller@b0a8000 {
|
|
- compatible = "qcom,kpss-acc-v1";
|
|
+ compatible = "qcom,kpss-acc-v2";
|
|
reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
|
|
};
|
|
|
|
acc3: clock-controller@b0b8000 {
|
|
- compatible = "qcom,kpss-acc-v1";
|
|
+ compatible = "qcom,kpss-acc-v2";
|
|
reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
|
|
};
|
|
|
|
@@ -308,6 +318,12 @@
|
|
regulator;
|
|
};
|
|
|
|
+ saw_l2: regulator@b012000 {
|
|
+ compatible = "qcom,saw2";
|
|
+ reg = <0xb012000 0x1000>;
|
|
+ regulator;
|
|
+ };
|
|
+
|
|
serial@78af000 {
|
|
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
|
reg = <0x78af000 0x200>;
|