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7d256aff7b
The previous iteration of MediaTek's PHY patches caused various weird bugs. Drop culprit patch 733-10-net-phy-mediatek-Extend-1G-TX-RX-link-pulse-time.patch and use the most recent iteration of the patchset which has been posted to the netdev mailing list. Link: https://patchwork.kernel.org/project/netdevbpf/list/?series=895513&state=* Fixes: #16448 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
63 lines
2.1 KiB
Diff
63 lines
2.1 KiB
Diff
From 61bcabdb69418215ea05bdc48cb88459d757f505 Mon Sep 17 00:00:00 2001
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From: "SkyLake.Huang" <skylake.huang@mediatek.com>
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Date: Fri, 4 Oct 2024 18:24:06 +0800
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Subject: [PATCH 2/9] net: phy: mediatek: Fix spelling errors and rearrange
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variables
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This patch fixes spelling errors which comes from mediatek-ge-soc.c and
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rearrange variables with reverse Xmas tree order.
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Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
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---
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drivers/net/phy/mediatek/mtk-ge-soc.c | 19 ++++++++++---------
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1 file changed, 10 insertions(+), 9 deletions(-)
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--- a/drivers/net/phy/mediatek/mtk-ge-soc.c
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+++ b/drivers/net/phy/mediatek/mtk-ge-soc.c
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@@ -408,16 +408,17 @@ static int tx_offset_cal_efuse(struct ph
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static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf)
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{
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- int i;
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- int bias[16] = {};
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- const int vals_9461[16] = { 7, 1, 4, 7,
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- 7, 1, 4, 7,
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- 7, 1, 4, 7,
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- 7, 1, 4, 7 };
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const int vals_9481[16] = { 10, 6, 6, 10,
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10, 6, 6, 10,
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10, 6, 6, 10,
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10, 6, 6, 10 };
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+ const int vals_9461[16] = { 7, 1, 4, 7,
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+ 7, 1, 4, 7,
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+ 7, 1, 4, 7,
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+ 7, 1, 4, 7 };
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+ int bias[16] = {};
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+ int i;
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+
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switch (phydev->drv->phy_id) {
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case MTK_GPHY_ID_MT7981:
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/* We add some calibration to efuse values
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@@ -1069,10 +1070,10 @@ static int start_cal(struct phy_device *
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static int mt798x_phy_calibration(struct phy_device *phydev)
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{
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+ struct nvmem_cell *cell;
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int ret = 0;
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- u32 *buf;
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size_t len;
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- struct nvmem_cell *cell;
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+ u32 *buf;
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cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data");
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if (IS_ERR(cell)) {
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@@ -1415,7 +1416,7 @@ static int mt7988_phy_probe_shared(struc
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* LED_C and LED_D respectively. At the same time those pins are used to
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* bootstrap configuration of the reference clock source (LED_A),
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* DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D).
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- * In practise this is done using a LED and a resistor pulling the pin
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+ * In practice this is done using a LED and a resistor pulling the pin
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* either to GND or to VIO.
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* The detected value at boot time is accessible at run-time using the
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* TPBANK0 register located in the gpio base of the pinctrl, in order
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