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eb13076e77
The upstream solution to define the MDIO bus in DT is a bit more strict than our previous downstream solution doing the same thing and now requires switch PHYs to be referenced in DT as well. Arınç Ünal told us in #15141: "With [the now upstream patch written by him which we backported], the switch MDIO bus won't be assigned to ds->user_mii_bus when the switch MDIO bus is defined on the device tree anymore. This was not the case with the downstream patch. When ds->user_mii_bus is populated, DSA will 1:1 map the port with PHY. Meaning port with address 1 will be mapped to PHY with address 1. Because that ds->user_mii_bus is not populated when the switch MDIO bus is defined on the device tree, on every port node, the PHY address must be supplied by the phy-handle property." Add those phy-handles to affected devices' DT. Fixes:4354b34f6f("generic: 6.6: sync mt7530 DSA driver with upstream") Fixes:401a6ccfaf("generic: 6.1: sync mt7530 DSA driver with upstream") Signed-off-by: Daniel Golle <daniel@makrotopia.org>
416 lines
7.6 KiB
Plaintext
416 lines
7.6 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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#include "mt7986a.dtsi"
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/ {
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model = "ASUS TUF-AX4200";
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compatible = "asus,tuf-ax4200", "mediatek,mt7986a";
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aliases {
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serial0 = &uart0;
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label-mac-device = &gmac0;
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led-boot = &led_system;
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led-failsafe = &led_system;
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led-running = &led_system;
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led-upgrade = &led_system;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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bootargs-override = "";
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};
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memory {
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reg = <0 0x40000000 0 0x20000000>;
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&pio 9 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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mesh {
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label = "wps";
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gpios = <&pio 10 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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};
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};
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leds {
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compatible = "gpio-leds";
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wlan24 {
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label = "white:wlan24";
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gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "phy0tpt";
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};
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wlan5 {
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label = "white:wlan5";
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gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "phy1tpt";
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};
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led_system: system {
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label = "white:system";
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gpios = <&pio 11 GPIO_ACTIVE_HIGH>;
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};
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wan-red {
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function = LED_FUNCTION_WAN;
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color = <LED_COLOR_ID_RED>;
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gpios = <&pio 12 GPIO_ACTIVE_LOW>;
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};
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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reg_5v: regulator-5v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-5V";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&crypto {
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status = "okay";
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};
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ð {
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status = "okay";
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gmac0: mac@0 {
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/* LAN */
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compatible = "mediatek,eth-mac";
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reg = <0>;
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nvmem-cells = <&macaddr_factory_4>;
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nvmem-cell-names = "mac-address";
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phy-mode = "2500base-x";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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gmac1: mac@1 {
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/* WAN */
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compatible = "mediatek,eth-mac";
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reg = <1>;
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phy-mode = "2500base-x";
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phy-handle = <&phy6>;
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};
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mdio: mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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&mdio {
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phy6: phy@6 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <6>;
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reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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reset-deassert-us = <10000>;
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/* LED0: CONN (WAN white) */
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mxl,led-config = <0x03f0 0x0 0x0 0x0>;
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};
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switch: switch@1f {
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compatible = "mediatek,mt7531";
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reg = <31>;
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reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
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reset-assert-us = <10000>;
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reset-deassert-us = <10000>;
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};
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};
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&pio {
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spi_flash_pins: spi-flash-pins-33-to-38 {
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mux {
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function = "spi";
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groups = "spi0", "spi0_wp_hold";
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};
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conf-pu {
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pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
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drive-strength = <8>;
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mediatek,pull-up-adv = <0>; /* bias-disable */
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};
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conf-pd {
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pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
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drive-strength = <8>;
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mediatek,pull-down-adv = <0>; /* bias-disable */
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};
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};
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wf_2g_5g_pins: wf_2g_5g-pins {
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mux {
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function = "wifi";
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groups = "wf_2g", "wf_5g";
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};
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conf {
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pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
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"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
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"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
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"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
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"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
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"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
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"WF1_TOP_CLK", "WF1_TOP_DATA";
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drive-strength = <4>;
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};
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};
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wf_dbdc_pins: wf-dbdc-pins {
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mux {
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function = "wifi";
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groups = "wf_dbdc";
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};
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conf {
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pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
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"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
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"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
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"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
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"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
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"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
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"WF1_TOP_CLK", "WF1_TOP_DATA";
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drive-strength = <4>;
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};
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};
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};
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi_flash_pins>;
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status = "okay";
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spi_nand_flash: flash@0 {
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compatible = "spi-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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spi-max-frequency = <20000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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/*
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* ASUS bootloader tries to replace the partitions defined in
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* Device Tree and by that also deletes all additional properties
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* needed for UBI and NVMEM-on-UBI.
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* Prevent this from happening by tricking the loader to delete and
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* replace a bait node instead.
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*/
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partitions: dummy {
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compatible = "u-boot-dummy-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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reg = <0x0 0x0>;
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label = "remove_me";
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};
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};
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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reg = <0x0 0x400000>;
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label = "bootloader";
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read-only;
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};
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partition@400000 {
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compatible = "linux,ubi";
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reg = <0x400000 0xfc00000>;
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label = "UBI_DEV";
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volumes {
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ubi_factory: ubi-volume-factory {
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volname = "Factory";
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};
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};
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};
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};
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};
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};
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&ubi_factory {
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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eeprom_factory_0: eeprom@0 {
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reg = <0x0 0x1000>;
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};
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macaddr_factory_4: macaddr@4 {
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reg = <0x4 0x6>;
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};
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};
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};
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&switch {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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label = "lan1";
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phy-handle = <&swphy1>;
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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phy-handle = <&swphy2>;
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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phy-handle = <&swphy3>;
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};
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port@4 {
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reg = <4>;
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label = "lan4";
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phy-handle = <&swphy4>;
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};
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port@6 {
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reg = <6>;
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label = "cpu";
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ethernet = <&gmac0>;
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phy-mode = "2500base-x";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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swphy1: phy@1 {
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reg = <1>;
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mediatek,led-config = <
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0x21 0x8009 /* BASIC_CTRL */
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0x22 0x0c00 /* ON_DURATION */
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0x23 0x1400 /* BLINK_DURATION */
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0x24 0x8000 /* LED0_ON_CTRL */
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0x25 0x0000 /* LED0_BLINK_CTRL */
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0x26 0xc007 /* LED1_ON_CTRL */
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0x27 0x003f /* LED1_BLINK_CTRL */
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>;
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};
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swphy2: phy@2 {
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reg = <2>;
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mediatek,led-config = <
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0x21 0x8009 /* BASIC_CTRL */
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0x22 0x0c00 /* ON_DURATION */
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0x23 0x1400 /* BLINK_DURATION */
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0x24 0x8000 /* LED0_ON_CTRL */
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0x25 0x0000 /* LED0_BLINK_CTRL */
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0x26 0xc007 /* LED1_ON_CTRL */
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0x27 0x003f /* LED1_BLINK_CTRL */
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>;
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};
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swphy3: phy@3 {
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reg = <3>;
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mediatek,led-config = <
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0x21 0x8009 /* BASIC_CTRL */
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0x22 0x0c00 /* ON_DURATION */
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0x23 0x1400 /* BLINK_DURATION */
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0x24 0x8000 /* LED0_ON_CTRL */
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0x25 0x0000 /* LED0_BLINK_CTRL */
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0x26 0xc007 /* LED1_ON_CTRL */
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0x27 0x003f /* LED1_BLINK_CTRL */
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>;
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};
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swphy4: phy@4 {
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reg = <4>;
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mediatek,led-config = <
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0x21 0x8009 /* BASIC_CTRL */
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0x22 0x0c00 /* ON_DURATION */
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0x23 0x1400 /* BLINK_DURATION */
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0x24 0x8000 /* LED0_ON_CTRL */
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0x25 0x0000 /* LED0_BLINK_CTRL */
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0x26 0xc007 /* LED1_ON_CTRL */
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0x27 0x003f /* LED1_BLINK_CTRL */
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>;
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};
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};
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};
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&watchdog {
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status = "okay";
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};
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&wifi {
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nvmem-cells = <&eeprom_factory_0>;
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nvmem-cell-names = "eeprom";
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pinctrl-0 = <&wf_2g_5g_pins>;
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pinctrl-1 = <&wf_dbdc_pins>;
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pinctrl-names = "default", "dbdc";
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status = "okay";
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};
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&trng {
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status = "okay";
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};
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&uart0 {
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status = "okay";
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};
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&ssusb {
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vusb33-supply = <®_3p3v>;
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vbus-supply = <®_5v>;
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status = "okay";
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};
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&usb_phy {
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status = "okay";
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};
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