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b04f245c39
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.23 Removed upstreamed: pending-6.6/735-net-mediatek-mtk_eth_soc-release-MAC_MCR_FORCE_LINK-.patch[1] pending-6.6/736-net-ethernet-mtk_eth_soc-fix-PPE-hanging-issue.patch[2] mediatek/patches-6.6/232-clk-mediatek-mt7981-topckgen-flag-SGM_REG_SEL-as-cri.patch[3] Manually rebased: mediatek/patches-6.6/100-dts-update-mt7622-rfb1.patch Added: generic/backports-6.6/981-mtd-spinand-Add-support-for-5-byte-IDs.patch[4] All other patches automatically rebased. 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.23&id=1f32abb474c1c9bdb21d9eda74c325a0b3a162e5 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.23&id=943c14ece95eb1cf98d477462aebcbfdfd714633 3. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.23&id=6ff01b314149d1cf59caebc29384f0beed21cba4 4. See comments in https://github.com/openwrt/openwrt/pull/14992 regarding broken flogic/xiaomi_redmi-router-ax6000-ubootmod Build system: x86/64 Build-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, flogic/glinet_gl-mt6000 Run-tested: x86/64/AMD Cezannei, flogic/xiaomi_redmi-router-ax6000-ubootmod, flogic/glinet_gl-mt6000 Signed-off-by: John Audia <therealgraysky@proton.me>
131 lines
4.1 KiB
Diff
131 lines
4.1 KiB
Diff
From bfd3acc428085742d754a6d328d1a93ebf9451df Mon Sep 17 00:00:00 2001
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From: "SkyLake.Huang" <skylake.huang@mediatek.com>
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Date: Thu, 23 Jun 2022 18:29:51 +0800
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Subject: [PATCH 1/6] drivers: spi-mt65xx: Move chip_config to driver's private
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data
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Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
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---
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drivers/spi/spi-mt65xx.c | 29 +++++++++---------------
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include/linux/platform_data/spi-mt65xx.h | 17 --------------
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2 files changed, 11 insertions(+), 35 deletions(-)
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delete mode 100644 include/linux/platform_data/spi-mt65xx.h
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--- a/drivers/spi/spi-mt65xx.c
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+++ b/drivers/spi/spi-mt65xx.c
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@@ -14,7 +14,6 @@
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#include <linux/of.h>
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#include <linux/gpio/consumer.h>
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#include <linux/platform_device.h>
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-#include <linux/platform_data/spi-mt65xx.h>
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#include <linux/pm_runtime.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi-mem.h>
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@@ -171,6 +170,8 @@ struct mtk_spi {
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struct device *dev;
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dma_addr_t tx_dma;
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dma_addr_t rx_dma;
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+ u32 sample_sel;
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+ u32 get_tick_dly;
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};
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static const struct mtk_spi_compatible mtk_common_compat;
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@@ -216,15 +217,6 @@ static const struct mtk_spi_compatible m
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.no_need_unprepare = true,
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};
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-/*
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- * A piece of default chip info unless the platform
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- * supplies it.
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- */
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-static const struct mtk_chip_config mtk_default_chip_info = {
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- .sample_sel = 0,
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- .tick_delay = 0,
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-};
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-
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static const struct of_device_id mtk_spi_of_match[] = {
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{ .compatible = "mediatek,spi-ipm",
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.data = (void *)&mtk_ipm_compat,
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@@ -352,7 +344,6 @@ static int mtk_spi_hw_init(struct spi_ma
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{
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u16 cpha, cpol;
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u32 reg_val;
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- struct mtk_chip_config *chip_config = spi->controller_data;
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struct mtk_spi *mdata = spi_master_get_devdata(master);
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cpha = spi->mode & SPI_CPHA ? 1 : 0;
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@@ -402,7 +393,7 @@ static int mtk_spi_hw_init(struct spi_ma
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else
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reg_val &= ~SPI_CMD_CS_POL;
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- if (chip_config->sample_sel)
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+ if (mdata->sample_sel)
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reg_val |= SPI_CMD_SAMPLE_SEL;
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else
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reg_val &= ~SPI_CMD_SAMPLE_SEL;
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@@ -429,20 +420,20 @@ static int mtk_spi_hw_init(struct spi_ma
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if (mdata->dev_comp->ipm_design) {
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reg_val = readl(mdata->base + SPI_CMD_REG);
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reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK;
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- reg_val |= ((chip_config->tick_delay & 0x7)
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+ reg_val |= ((mdata->get_tick_dly & 0x7)
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<< SPI_CMD_IPM_GET_TICKDLY_OFFSET);
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writel(reg_val, mdata->base + SPI_CMD_REG);
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} else {
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reg_val = readl(mdata->base + SPI_CFG1_REG);
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reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
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- reg_val |= ((chip_config->tick_delay & 0x7)
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+ reg_val |= ((mdata->get_tick_dly & 0x7)
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<< SPI_CFG1_GET_TICK_DLY_OFFSET);
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writel(reg_val, mdata->base + SPI_CFG1_REG);
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}
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} else {
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reg_val = readl(mdata->base + SPI_CFG1_REG);
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reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;
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- reg_val |= ((chip_config->tick_delay & 0x3)
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+ reg_val |= ((mdata->get_tick_dly & 0x3)
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<< SPI_CFG1_GET_TICK_DLY_OFFSET_V1);
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writel(reg_val, mdata->base + SPI_CFG1_REG);
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}
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@@ -732,9 +723,6 @@ static int mtk_spi_setup(struct spi_devi
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{
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struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
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- if (!spi->controller_data)
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- spi->controller_data = (void *)&mtk_default_chip_info;
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-
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if (mdata->dev_comp->need_pad_sel && spi_get_csgpiod(spi, 0))
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/* CS de-asserted, gpiolib will handle inversion */
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gpiod_direction_output(spi_get_csgpiod(spi, 0), 0);
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@@ -1140,6 +1128,10 @@ static int mtk_spi_probe(struct platform
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mdata = spi_master_get_devdata(master);
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mdata->dev_comp = device_get_match_data(dev);
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+ /* Set device configs to default first. Calibrate it later. */
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+ mdata->sample_sel = 0;
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+ mdata->get_tick_dly = 2;
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+
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if (mdata->dev_comp->enhance_timing)
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master->mode_bits |= SPI_CS_HIGH;
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--- a/include/linux/platform_data/spi-mt65xx.h
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+++ /dev/null
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@@ -1,17 +0,0 @@
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-/* SPDX-License-Identifier: GPL-2.0-only */
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-/*
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- * MTK SPI bus driver definitions
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- *
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- * Copyright (c) 2015 MediaTek Inc.
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- * Author: Leilk Liu <leilk.liu@mediatek.com>
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- */
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-
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-#ifndef ____LINUX_PLATFORM_DATA_SPI_MTK_H
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-#define ____LINUX_PLATFORM_DATA_SPI_MTK_H
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-
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-/* Board specific platform_data */
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-struct mtk_chip_config {
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- u32 sample_sel;
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- u32 tick_delay;
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-};
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-#endif
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