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b40e6bc55f
In ath79, for several SoCs the console bootargs are defined to the
very same value in every device's DTS. Consolidate these definitions
in the SoC dtsi files and drop further redundant definitions elsewhere.
The only device without any bootargs set has been OpenMesh OM5P-AC V2.
This will now inherit the setting from qca955x.dtsi
While this is a cosmetic change, backporting it to 19.07 will be a
major help for anyone doing backports of device support. Without it,
every backporter would have to remember to manually add the chosen node
to the device's DTS.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
(cherry picked from commit 635f111148)
321 lines
5.9 KiB
Plaintext
321 lines
5.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include <dt-bindings/clock/ath79-clk.h>
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#include "ath79.dtsi"
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/ {
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compatible = "qca,qca9560";
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#address-cells = <1>;
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#size-cells = <1>;
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chosen {
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bootargs = "console=ttyS0,115200n8";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "mips,mips74Kc";
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clocks = <&pll ATH79_CLK_CPU>;
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reg = <0>;
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};
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};
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extosc: ref {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "ref";
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clock-frequency = <25000000>;
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};
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ahb {
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apb {
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ddr_ctrl: memory-controller@18000000 {
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compatible = "qca,qca9560-ddr-controller",
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"qca,ar7240-ddr-controller";
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reg = <0x18000000 0x100>;
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#qca,ddr-wb-channel-cells = <1>;
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};
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uart: uart@18020000 {
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compatible = "ns16550a";
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reg = <0x18020000 0x20>;
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interrupts = <3>;
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clocks = <&pll ATH79_CLK_REF>;
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clock-names = "uart";
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reg-io-width = <4>;
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reg-shift = <2>;
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no-loopback-test;
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status = "disabled";
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};
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gpio: gpio@18040000 {
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compatible = "qca,qca9560-gpio",
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"qca,ar9340-gpio";
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reg = <0x18040000 0x28>;
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interrupts = <2>;
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ngpios = <24>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pinmux: pinmux@1804002c {
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compatible = "pinctrl-single";
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reg = <0x1804002c 0x44>;
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#size-cells = <0>;
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pinctrl-single,bit-per-mux;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x1>;
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#pinctrl-cells = <2>;
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jtag_disable_pins: pinmux_jtag_disable_pins {
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pinctrl-single,bits = <0x40 0x2 0x2>;
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};
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};
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pll: pll-controller@18050000 {
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compatible = "qca,qca9560-pll", "syscon";
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reg = <0x18050000 0x50>;
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#clock-cells = <1>;
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clock-output-names = "cpu", "ddr", "ahb";
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clocks = <&extosc>;
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};
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wdt: wdt@18060008 {
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compatible = "qca,ar7130-wdt";
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reg = <0x18060008 0x8>;
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interrupts = <4>;
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clocks = <&pll ATH79_CLK_AHB>;
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clock-names = "wdt";
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};
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rst: reset-controller@1806001c {
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compatible = "qca,qca9560-reset",
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"qca,ar7100-reset";
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reg = <0x1806001c 0x4>;
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#reset-cells = <1>;
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interrupt-parent = <&cpuintc>;
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intc3: interrupt-controller {
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compatible = "qca,ar9340-intc";
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interrupt-parent = <&cpuintc>;
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interrupts = <3>;
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interrupt-controller;
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#interrupt-cells = <1>;
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qca,int-status-addr = <0xac>;
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qca,pending-bits = <0x1f000>, /* pcie rc */
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<0x1000000>, /* usb1 */
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<0x10000000>; /* usb2 */
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};
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};
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rst2: reset-controller@180600c0 {
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compatible = "qca,qca9560-reset",
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"qca,ar7100-reset",
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"simple-bus";
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reg = <0x180600c0 0x4>;
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#reset-cells = <1>;
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};
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};
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gmac: gmac@18070000 {
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compatible = "qca,qca9560-gmac";
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reg = <0x18070000 0x64>;
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};
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wmac: wmac@18100000 {
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compatible = "qca,qca9560-wmac";
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reg = <0x18100000 0x10000>;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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status = "disabled";
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};
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pcie: pcie-controller@18250000 {
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compatible = "qcom,ar7240-pci";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x0 0x0>;
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reg = <0x18250000 0x1000>, /* CRP */
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<0x18280000 0x100>, /* CTRL */
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<0x16000000 0x1000>; /* CFG */
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reg-names = "crp_base", "ctrl_base", "cfg_base";
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ranges = <0x2000000 0 0x12000000 0x12000000 0 0x02000000 /* pci memory */
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0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
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interrupt-parent = <&intc3>;
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interrupts = <0>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 1>;
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interrupt-map = <0 0 0 0 &pcie 0>;
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status = "disabled";
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};
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usb0: usb@1b000000 {
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compatible = "generic-ehci";
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reg = <0x1b000000 0x1d8>;
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interrupt-parent = <&intc3>;
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interrupts = <1>;
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resets = <&rst 5>;
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reset-names = "usb-host";
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has-transaction-translator;
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caps-offset = <0x100>;
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phy-names = "usb-phy0";
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phys = <&usb_phy0>;
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status = "disabled";
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};
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usb1: usb@1b400000 {
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compatible = "generic-ehci";
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reg = <0x1b400000 0x1d8>;
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interrupt-parent = <&intc3>;
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interrupts = <2>;
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resets = <&rst2 5>;
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reset-names = "usb-host";
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has-transaction-translator;
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caps-offset = <0x100>;
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phy-names = "usb-phy1";
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phys = <&usb_phy1>;
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status = "disabled";
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};
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spi: spi@1f000000 {
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compatible = "qca,qca9560-spi", "qca,ar7100-spi";
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reg = <0x1f000000 0x10>;
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clocks = <&pll ATH79_CLK_AHB>;
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clock-names = "ahb";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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usb_phy0: usb-phy {
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compatible = "qca,qca9560-usb-phy", "qca,ar7200-usb-phy";
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reset-names = "usb-phy", "usb-suspend-override";
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resets = <&rst 4>, <&rst 3>;
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#phy-cells = <0>;
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status = "disabled";
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};
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usb_phy1: usb-phy {
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compatible = "qca,qca9560-usb-phy", "qca,ar7200-usb-phy";
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reset-names = "usb-phy", "usb-suspend-override";
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resets = <&rst2 4>, <&rst2 3>;
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#phy-cells = <0>;
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status = "disabled";
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};
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};
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&mdio0 {
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resets = <&rst 22>;
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reset-names = "mdio";
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};
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ð0 {
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compatible = "qca,qca9560-eth", "syscon";
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pll-data = <0x03000000 0x00000101 0x00001919>;
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pll-reg = <0 0x48 0>;
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pll-handle = <&pll>;
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resets = <&rst 9>;
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reset-names = "mac";
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};
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&mdio1 {
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status = "okay";
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resets = <&rst 23>;
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reset-names = "mdio";
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builtin-switch;
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builtin_switch: switch0@1f {
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compatible = "qca,ar8229";
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reg = <0x1f>;
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resets = <&rst 8>;
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reset-names = "switch";
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phy-mode = "gmii";
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qca,phy4-mii-enable;
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qca,mib-poll-interval = <500>;
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mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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swphy0: ethernet-phy@0 {
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reg = <0>;
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phy-mode = "mii";
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};
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swphy4: ethernet-phy@4 {
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reg = <4>;
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phy-mode = "mii";
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};
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};
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};
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};
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ð1 {
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compatible = "qca,qca9560-eth", "syscon";
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phy-mode = "gmii";
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resets = <&rst 13>;
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reset-names = "mac";
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status = "disabled";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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