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c2c741ccce
Initial backport of at803x PHY driver cleanup. This is in preparation for split and addition of new PHY Family based on at803x needed for ipq807x and other IPQ Series SoC. Other affected patch are automatically refreshed with make target/linux/refresh Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
153 lines
6.2 KiB
Diff
153 lines
6.2 KiB
Diff
From 7961ef1fa10ec35ad6923fb5751877116e4b035b Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Tue, 19 Dec 2023 21:21:24 +0100
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Subject: [PATCH] net: phy: at803x: better align function varibles to open
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parenthesis
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Better align function variables to open parenthesis as suggested by
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checkpatch script for qca808x function to make code cleaner.
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For cable_test_get_status function some additional rework was needed to
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handle too long functions.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/phy/at803x.c | 67 ++++++++++++++++++++++------------------
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1 file changed, 37 insertions(+), 30 deletions(-)
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--- a/drivers/net/phy/at803x.c
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+++ b/drivers/net/phy/at803x.c
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@@ -1781,27 +1781,27 @@ static int qca808x_phy_fast_retrain_conf
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return ret;
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phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,
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- QCA808X_TOP_OPTION1_DATA);
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+ QCA808X_TOP_OPTION1_DATA);
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phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,
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- QCA808X_MSE_THRESHOLD_20DB_VALUE);
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+ QCA808X_MSE_THRESHOLD_20DB_VALUE);
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phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,
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- QCA808X_MSE_THRESHOLD_17DB_VALUE);
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+ QCA808X_MSE_THRESHOLD_17DB_VALUE);
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phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,
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- QCA808X_MSE_THRESHOLD_27DB_VALUE);
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+ QCA808X_MSE_THRESHOLD_27DB_VALUE);
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phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,
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- QCA808X_MSE_THRESHOLD_28DB_VALUE);
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+ QCA808X_MSE_THRESHOLD_28DB_VALUE);
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phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1,
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- QCA808X_MMD3_DEBUG_1_VALUE);
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+ QCA808X_MMD3_DEBUG_1_VALUE);
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phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4,
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- QCA808X_MMD3_DEBUG_4_VALUE);
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+ QCA808X_MMD3_DEBUG_4_VALUE);
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phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5,
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- QCA808X_MMD3_DEBUG_5_VALUE);
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+ QCA808X_MMD3_DEBUG_5_VALUE);
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phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3,
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- QCA808X_MMD3_DEBUG_3_VALUE);
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+ QCA808X_MMD3_DEBUG_3_VALUE);
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phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6,
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- QCA808X_MMD3_DEBUG_6_VALUE);
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+ QCA808X_MMD3_DEBUG_6_VALUE);
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phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2,
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- QCA808X_MMD3_DEBUG_2_VALUE);
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+ QCA808X_MMD3_DEBUG_2_VALUE);
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return 0;
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}
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@@ -1838,13 +1838,14 @@ static int qca808x_config_init(struct ph
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/* Active adc&vga on 802.3az for the link 1000M and 100M */
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ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
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- QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
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+ QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
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if (ret)
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return ret;
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/* Adjust the threshold on 802.3az for the link 1000M */
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ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
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- QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, QCA808X_MMD3_AZ_TRAINING_VAL);
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+ QCA808X_PHY_MMD3_AZ_TRAINING_CTRL,
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+ QCA808X_MMD3_AZ_TRAINING_VAL);
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if (ret)
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return ret;
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@@ -1870,7 +1871,8 @@ static int qca808x_config_init(struct ph
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/* Configure adc threshold as 100mv for the link 10M */
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return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
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- QCA808X_ADC_THRESHOLD_MASK, QCA808X_ADC_THRESHOLD_100MV);
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+ QCA808X_ADC_THRESHOLD_MASK,
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+ QCA808X_ADC_THRESHOLD_100MV);
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}
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static int qca808x_read_status(struct phy_device *phydev)
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@@ -1883,7 +1885,7 @@ static int qca808x_read_status(struct ph
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return ret;
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linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising,
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- ret & MDIO_AN_10GBT_STAT_LP2_5G);
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+ ret & MDIO_AN_10GBT_STAT_LP2_5G);
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ret = genphy_read_status(phydev);
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if (ret)
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@@ -1913,7 +1915,7 @@ static int qca808x_read_status(struct ph
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*/
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if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
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if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR ||
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- qca808x_is_prefer_master(phydev)) {
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+ qca808x_is_prefer_master(phydev)) {
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qca808x_phy_ms_seed_enable(phydev, false);
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} else {
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qca808x_phy_ms_seed_enable(phydev, true);
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@@ -2070,18 +2072,22 @@ static int qca808x_cable_test_get_status
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ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D,
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qca808x_cable_test_result_trans(pair_d));
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- if (qca808x_cdt_fault_length_valid(pair_a))
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- ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A,
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- qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A));
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- if (qca808x_cdt_fault_length_valid(pair_b))
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- ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B,
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- qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B));
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- if (qca808x_cdt_fault_length_valid(pair_c))
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- ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C,
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- qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C));
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- if (qca808x_cdt_fault_length_valid(pair_d))
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- ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D,
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- qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D));
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+ if (qca808x_cdt_fault_length_valid(pair_a)) {
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+ val = qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A);
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+ ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A, val);
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+ }
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+ if (qca808x_cdt_fault_length_valid(pair_b)) {
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+ val = qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B);
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+ ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_B, val);
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+ }
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+ if (qca808x_cdt_fault_length_valid(pair_c)) {
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+ val = qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C);
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+ ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_C, val);
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+ }
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+ if (qca808x_cdt_fault_length_valid(pair_d)) {
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+ val = qca808x_cdt_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D);
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+ ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_D, val);
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+ }
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*finished = true;
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@@ -2148,8 +2154,9 @@ static void qca808x_link_change_notify(s
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* the interface device address is always phy address added by 1.
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*/
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mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1,
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- MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,
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- QCA8081_PHY_FIFO_RSTN, phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
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+ MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,
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+ QCA8081_PHY_FIFO_RSTN,
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+ phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
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}
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static struct phy_driver at803x_driver[] = {
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