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bb1eb5e8e6
1. Add support for Marvell CN9130 SoC
2. Add support for CP115,and create an armada-cp11x.dtsi file which will be used to instantiate both CP110 and CP115
3. Add support for AP807/AP807-quad,AP807 is a major component of CN9130 SoC series
4. Drop PCIe I/O ranges from CP11x file and externalize PCIe macros from CP11x file
Signed-off-by: Ian Chang <ianchang@ieiworld.com>
(cherry picked from commit c98ddf0f01)
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
88 lines
2.3 KiB
Diff
88 lines
2.3 KiB
Diff
From 30d53abdc60a6515f02f181e7c39b7b23d5fb3aa Mon Sep 17 00:00:00 2001
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From: Grzegorz Jaszczyk <jaz@semihalf.com>
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Date: Fri, 4 Oct 2019 16:27:27 +0200
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Subject: [PATCH] arm64: dts: marvell: Add AP807-quad cache description
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Adding appropriate entries to device-tree allows the cache description
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to show up in sysfs under: /sys/devices/system/cpu/cpuX/cache/.
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Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
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---
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.../boot/dts/marvell/armada-ap807-quad.dtsi | 42 +++++++++++++++++++
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1 file changed, 42 insertions(+)
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--- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
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+++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
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@@ -22,6 +22,13 @@
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enable-method = "psci";
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#cooling-cells = <2>;
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clocks = <&cpu_clk 0>;
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+ i-cache-size = <0xc000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <256>;
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+ d-cache-size = <0x8000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <256>;
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+ next-level-cache = <&l2_0>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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@@ -30,6 +37,13 @@
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enable-method = "psci";
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#cooling-cells = <2>;
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clocks = <&cpu_clk 0>;
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+ i-cache-size = <0xc000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <256>;
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+ d-cache-size = <0x8000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <256>;
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+ next-level-cache = <&l2_0>;
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};
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cpu2: cpu@100 {
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device_type = "cpu";
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@@ -38,6 +52,13 @@
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enable-method = "psci";
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#cooling-cells = <2>;
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clocks = <&cpu_clk 1>;
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+ i-cache-size = <0xc000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <256>;
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+ d-cache-size = <0x8000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <256>;
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+ next-level-cache = <&l2_1>;
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};
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cpu3: cpu@101 {
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device_type = "cpu";
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@@ -46,6 +67,27 @@
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enable-method = "psci";
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#cooling-cells = <2>;
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clocks = <&cpu_clk 1>;
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+ i-cache-size = <0xc000>;
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+ i-cache-line-size = <64>;
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+ i-cache-sets = <256>;
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+ d-cache-size = <0x8000>;
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+ d-cache-line-size = <64>;
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+ d-cache-sets = <256>;
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+ next-level-cache = <&l2_1>;
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+ };
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+
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+ l2_0: l2-cache0 {
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+ compatible = "cache";
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+ cache-size = <0x80000>;
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+ cache-line-size = <64>;
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+ cache-sets = <512>;
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+ };
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+
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+ l2_1: l2-cache1 {
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+ compatible = "cache";
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+ cache-size = <0x80000>;
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+ cache-line-size = <64>;
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+ cache-sets = <512>;
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};
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};
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};
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