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4a281a7789
RISC-V is a new CPU architecture aimed to be fully free and open. This
target will add support for it, based on 5.15.
Supports running on:
- HiFive Unleashed - FU540, first generation
- HiFive Unmatched - FU740, current latest generation, PCIe
SD-card images are generated, where the partitions are required to have
specific type codes. As it is commonplace nowadays, OpenSBI is used as the
first stage, with U-boot following as the proper bootloader.
Specifications:
HiFive Unleashed:
- CPU: SiFive FU540 quad-core RISC-V (U54, RV64IMAFDC or RV64GC)
- Memory: 8Gb
- Ethernet: 1x 10/100/1000
- Console: via microUSB
HiFive Unmatched:
- CPU: SiFive FU740 quad-core RISC-V (U74, RV64IMAFDCB or RV64GCB)
- Memory: 16Gb
- Ethernet: 1x 10/100/1000
- USB: 4x USB 3.2
- PCIe: - 1x PCIe Gen3 x8
- 1x M.2 key M (PCIe x4)
- 1x M.2 Key E (PCIe x1 / USB2.0)
- Console: via microUSB
Installation:
Standard SD-card installation via dd-ing the generated image to
an SD-card of at least 256Mb.
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
(cherry picked from commit a3469a90c4)
50 lines
1.5 KiB
Diff
50 lines
1.5 KiB
Diff
From ab5c8f5492cce16ff2104393e2f1fa64a3ff6e88 Mon Sep 17 00:00:00 2001
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From: David Abdurachmanov <david.abdurachmanov@sifive.com>
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Date: Wed, 17 Feb 2021 06:06:14 -0800
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Subject: [PATCH 1/7] riscv: sifive: fu740: cpu{1,2,3,4} set compatible to
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sifive,u74-mc
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Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
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---
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arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 8 ++++----
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1 file changed, 4 insertions(+), 4 deletions(-)
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--- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
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+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
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@@ -39,7 +39,7 @@
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};
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};
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cpu1: cpu@1 {
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- compatible = "sifive,bullet0", "riscv";
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+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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@@ -63,7 +63,7 @@
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};
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};
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cpu2: cpu@2 {
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- compatible = "sifive,bullet0", "riscv";
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+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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@@ -87,7 +87,7 @@
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};
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};
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cpu3: cpu@3 {
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- compatible = "sifive,bullet0", "riscv";
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+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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@@ -111,7 +111,7 @@
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};
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};
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cpu4: cpu@4 {
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- compatible = "sifive,bullet0", "riscv";
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+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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