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e231cdd0c6
renumber patches for upcoming new device support Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> Link: https://github.com/openwrt/openwrt/pull/16185 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
249 lines
6.2 KiB
Diff
249 lines
6.2 KiB
Diff
From 8ca5e0e4d6ed084d2321584e8cdc8105c60b9aa1 Mon Sep 17 00:00:00 2001
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From: FUKAUMI Naoki <naoki@radxa.com>
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Date: Tue, 25 Jun 2024 05:45:29 +0900
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Subject: [PATCH] rockchip: add support for Radxa ROCK Pi E v3.0
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ROCK Pi E v3.0 uses DDR4 SDRAM instead of DDR3 SDRAM used in v1.2x.
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prepare new rk3328-rock-pi-e-v3.dts in u-boot which just includes
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upstream rk3328-rock-pi-e.dts.
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defconfig still uses
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CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock-pi-e.dtb"
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because v3.0 and prior are compatible.
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Suggested-by: Jonas Karlman <jonas@kwiboo.se>
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Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
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Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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---
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...dtsi => rk3328-rock-pi-e-base-u-boot.dtsi} | 1 -
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arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi | 47 +--------
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arch/arm/dts/rk3328-rock-pi-e-v3-u-boot.dtsi | 4 +
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arch/arm/dts/rk3328-rock-pi-e-v3.dts | 4 +
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board/rockchip/evb_rk3328/MAINTAINERS | 4 +-
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configs/rock-pi-e-v3-rk3328_defconfig | 97 +++++++++++++++++++
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6 files changed, 111 insertions(+), 46 deletions(-)
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copy arch/arm/dts/{rk3328-rock-pi-e-u-boot.dtsi => rk3328-rock-pi-e-base-u-boot.dtsi} (94%)
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rewrite arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi (88%)
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create mode 100644 arch/arm/dts/rk3328-rock-pi-e-v3-u-boot.dtsi
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create mode 100644 arch/arm/dts/rk3328-rock-pi-e-v3.dts
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create mode 100644 configs/rock-pi-e-v3-rk3328_defconfig
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--- a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
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+++ b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
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@@ -1,43 +1,4 @@
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// SPDX-License-Identifier: GPL-2.0+
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-/*
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- * (C) Copyright 2020 Radxa
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- */
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-#include "rk3328-u-boot.dtsi"
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+#include "rk3328-rock-pi-e-base-u-boot.dtsi"
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#include "rk3328-sdram-ddr3-666.dtsi"
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-
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-/ {
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- smbios {
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- compatible = "u-boot,sysinfo-smbios";
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-
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- smbios {
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- system {
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- manufacturer = "radxa";
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- product = "rock-pi-e_rk3328";
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- };
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-
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- baseboard {
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- manufacturer = "radxa";
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- product = "rock-pi-e_rk3328";
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- };
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-
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- chassis {
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- manufacturer = "radxa";
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- product = "rock-pi-e_rk3328";
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- };
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- };
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- };
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-};
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-
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-&u2phy_host {
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- phy-supply = <&vcc_host_5v>;
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-};
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-
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-&vcc_host_5v {
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- /delete-property/ regulator-always-on;
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- /delete-property/ regulator-boot-on;
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-};
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-
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-&vcc_sd {
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- bootph-pre-ram;
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-};
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--- /dev/null
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+++ b/arch/arm/dts/rk3328-rock-pi-e-base-u-boot.dtsi
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@@ -0,0 +1,42 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * (C) Copyright 2020 Radxa
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+ */
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+
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+#include "rk3328-u-boot.dtsi"
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+
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+/ {
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+ smbios {
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+ compatible = "u-boot,sysinfo-smbios";
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+
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+ smbios {
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+ system {
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+ manufacturer = "radxa";
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+ product = "rock-pi-e_rk3328";
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+ };
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+
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+ baseboard {
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+ manufacturer = "radxa";
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+ product = "rock-pi-e_rk3328";
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+ };
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+
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+ chassis {
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+ manufacturer = "radxa";
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+ product = "rock-pi-e_rk3328";
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+ };
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+ };
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+ };
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+};
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+
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+&u2phy_host {
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+ phy-supply = <&vcc_host_5v>;
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+};
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+
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+&vcc_host_5v {
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+ /delete-property/ regulator-always-on;
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+ /delete-property/ regulator-boot-on;
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+};
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+
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+&vcc_sd {
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+ bootph-pre-ram;
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+};
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--- /dev/null
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+++ b/arch/arm/dts/rk3328-rock-pi-e-v3-u-boot.dtsi
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@@ -0,0 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+
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+#include "rk3328-rock-pi-e-base-u-boot.dtsi"
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+#include "rk3328-sdram-ddr4-666.dtsi"
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--- /dev/null
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+++ b/arch/arm/dts/rk3328-rock-pi-e-v3.dts
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@@ -0,0 +1,4 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+
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+/dts-v1/;
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+#include "rk3328-rock-pi-e.dts"
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--- a/board/rockchip/evb_rk3328/MAINTAINERS
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+++ b/board/rockchip/evb_rk3328/MAINTAINERS
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@@ -64,5 +64,5 @@ M: Banglang Huang <banglang.huang@f
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R: Jonas Karlman <jonas@kwiboo.se>
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S: Maintained
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F: configs/rock-pi-e-rk3328_defconfig
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-F: arch/arm/dts/rk3328-rock-pi-e.dts
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-F: arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
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+F: configs/rock-pi-e-v3-rk3328_defconfig
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+F: arch/arm/dts/rk3328-rock-pi-e*
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--- /dev/null
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+++ b/configs/rock-pi-e-v3-rk3328_defconfig
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@@ -0,0 +1,97 @@
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+CONFIG_ARM=y
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+CONFIG_SKIP_LOWLEVEL_INIT=y
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+CONFIG_COUNTER_FREQUENCY=24000000
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+CONFIG_ARCH_ROCKCHIP=y
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+CONFIG_SPL_GPIO=y
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+CONFIG_NR_DRAM_BANKS=1
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+CONFIG_SF_DEFAULT_SPEED=20000000
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+CONFIG_ENV_OFFSET=0x3F8000
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+CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock-pi-e-v3"
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+CONFIG_DM_RESET=y
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+CONFIG_ROCKCHIP_RK3328=y
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+CONFIG_DEBUG_UART_BASE=0xFF130000
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+CONFIG_DEBUG_UART_CLOCK=24000000
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+CONFIG_SYS_LOAD_ADDR=0x800800
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+CONFIG_DEBUG_UART=y
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+CONFIG_FIT=y
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+CONFIG_FIT_VERBOSE=y
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+CONFIG_SPL_FIT_SIGNATURE=y
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+CONFIG_SPL_LOAD_FIT=y
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+CONFIG_LEGACY_IMAGE_FORMAT=y
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+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock-pi-e.dtb"
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+# CONFIG_DISPLAY_CPUINFO is not set
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+CONFIG_DISPLAY_BOARDINFO_LATE=y
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+CONFIG_SPL_MAX_SIZE=0x40000
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+CONFIG_SPL_PAD_TO=0x7f8000
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+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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+CONFIG_SPL_POWER=y
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+CONFIG_SPL_ATF=y
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+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
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+CONFIG_CMD_BOOTZ=y
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+CONFIG_CMD_GPIO=y
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+CONFIG_CMD_GPT=y
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+CONFIG_CMD_MMC=y
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+CONFIG_CMD_USB=y
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+CONFIG_CMD_TIME=y
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+CONFIG_CMD_REGULATOR=y
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+CONFIG_SPL_OF_CONTROL=y
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+CONFIG_TPL_OF_CONTROL=y
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+# CONFIG_OF_UPSTREAM is not set
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+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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+CONFIG_TPL_OF_PLATDATA=y
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+CONFIG_ENV_IS_IN_MMC=y
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+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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+CONFIG_SYS_MMC_ENV_DEV=1
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+CONFIG_TPL_DM=y
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+CONFIG_SPL_DM_SEQ_ALIAS=y
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+CONFIG_REGMAP=y
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+CONFIG_SPL_REGMAP=y
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+CONFIG_TPL_REGMAP=y
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+CONFIG_SYSCON=y
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+CONFIG_SPL_SYSCON=y
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+CONFIG_TPL_SYSCON=y
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+CONFIG_CLK=y
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+CONFIG_SPL_CLK=y
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+CONFIG_ROCKCHIP_GPIO=y
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+CONFIG_SYS_I2C_ROCKCHIP=y
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+CONFIG_MMC_DW=y
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+CONFIG_MMC_DW_ROCKCHIP=y
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+CONFIG_PHY_REALTEK=y
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+CONFIG_DM_MDIO=y
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+CONFIG_DM_ETH_PHY=y
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+CONFIG_PHY_GIGE=y
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+CONFIG_ETH_DESIGNWARE=y
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+CONFIG_GMAC_ROCKCHIP=y
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+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
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+CONFIG_PINCTRL=y
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+CONFIG_SPL_PINCTRL=y
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+CONFIG_DM_PMIC=y
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+CONFIG_PMIC_RK8XX=y
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+CONFIG_SPL_DM_REGULATOR=y
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+CONFIG_DM_REGULATOR_FIXED=y
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+CONFIG_SPL_DM_REGULATOR_FIXED=y
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+CONFIG_REGULATOR_RK8XX=y
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+CONFIG_PWM_ROCKCHIP=y
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+CONFIG_RAM=y
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+CONFIG_SPL_RAM=y
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+CONFIG_TPL_RAM=y
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+CONFIG_DM_RNG=y
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+CONFIG_RNG_ROCKCHIP=y
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+CONFIG_BAUDRATE=1500000
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+CONFIG_DEBUG_UART_SHIFT=2
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+CONFIG_SYS_NS16550_MEM32=y
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+CONFIG_SYSINFO=y
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+CONFIG_SYSINFO_SMBIOS=y
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+CONFIG_SYSRESET=y
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+# CONFIG_TPL_SYSRESET is not set
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+CONFIG_USB=y
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+CONFIG_USB_XHCI_HCD=y
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+CONFIG_USB_EHCI_HCD=y
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+CONFIG_USB_EHCI_GENERIC=y
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+CONFIG_USB_OHCI_HCD=y
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+CONFIG_USB_OHCI_GENERIC=y
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+CONFIG_USB_DWC3=y
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+CONFIG_USB_DWC3_GENERIC=y
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+CONFIG_SPL_TINY_MEMSET=y
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+CONFIG_TPL_TINY_MEMSET=y
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+CONFIG_ERRNO_STR=y
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