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127 lines
4.5 KiB
Diff
127 lines
4.5 KiB
Diff
From a05cd269cbf2623efe2499459efdd123ee04ab81 Mon Sep 17 00:00:00 2001
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From: P33M <P33M@github.com>
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Date: Wed, 4 Feb 2015 12:16:50 +0000
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Subject: [PATCH 105/114] dwc_otg: fixup read-modify-write in critical paths
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Be more careful about read-modify-write on registers that the FIQ
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also touches.
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---
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drivers/usb/host/dwc_otg/dwc_otg_hcd.c | 13 +++++++++---
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drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 30 +++++++++++++++++++++++++---
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drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c | 22 ++++++++++++++++----
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3 files changed, 55 insertions(+), 10 deletions(-)
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--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
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+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
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@@ -2447,9 +2447,16 @@ void dwc_otg_hcd_queue_transactions(dwc_
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*/
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gintmsk_data_t gintmsk = {.d32 = 0 };
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gintmsk.b.nptxfempty = 1;
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- DWC_MODIFY_REG32(&hcd->core_if->
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- core_global_regs->gintmsk, gintmsk.d32,
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- 0);
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+
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+ if (fiq_enable) {
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+ local_fiq_disable();
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+ fiq_fsm_spin_lock(&hcd->fiq_state->lock);
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+ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
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+ fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
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+ local_fiq_enable();
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+ } else {
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+ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
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+ }
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}
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}
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}
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--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
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+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
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@@ -165,7 +165,15 @@ int32_t dwc_otg_hcd_handle_intr(dwc_otg_
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gintmsk_data_t gintmsk = { .b.portintr = 1};
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retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
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- DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
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+ if (fiq_enable) {
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+ local_fiq_disable();
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+ fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
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+ DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
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+ fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
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+ local_fiq_enable();
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+ } else {
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+ DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
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+ }
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}
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if (gintsts.b.hcintr) {
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retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
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@@ -1069,7 +1077,15 @@ static void halt_channel(dwc_otg_hcd_t *
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* be processed.
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*/
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gintmsk.b.nptxfempty = 1;
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- DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
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+ if (fiq_enable) {
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+ local_fiq_disable();
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+ fiq_fsm_spin_lock(&hcd->fiq_state->lock);
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+ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
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+ fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
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+ local_fiq_enable();
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+ } else {
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+ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
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+ }
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} else {
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/*
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* Move the QH from the periodic queued schedule to
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@@ -1086,7 +1102,15 @@ static void halt_channel(dwc_otg_hcd_t *
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* processed.
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*/
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gintmsk.b.ptxfempty = 1;
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- DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
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+ if (fiq_enable) {
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+ local_fiq_disable();
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+ fiq_fsm_spin_lock(&hcd->fiq_state->lock);
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+ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
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+ fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
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+ local_fiq_enable();
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+ } else {
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+ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
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+ }
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}
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}
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}
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--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c
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+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c
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@@ -683,8 +683,15 @@ int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * h
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status = schedule_periodic(hcd, qh);
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if ( !hcd->periodic_qh_count ) {
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intr_mask.b.sofintr = 1;
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- DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk,
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- intr_mask.d32, intr_mask.d32);
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+ if (fiq_enable) {
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+ local_fiq_disable();
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+ fiq_fsm_spin_lock(&hcd->fiq_state->lock);
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+ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
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+ fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
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+ local_fiq_enable();
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+ } else {
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+ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
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+ }
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}
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hcd->periodic_qh_count++;
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}
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@@ -745,8 +752,15 @@ void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t
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hcd->periodic_qh_count--;
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if( !hcd->periodic_qh_count && !fiq_fsm_enable ) {
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intr_mask.b.sofintr = 1;
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- DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk,
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- intr_mask.d32, 0);
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+ if (fiq_enable) {
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+ local_fiq_disable();
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+ fiq_fsm_spin_lock(&hcd->fiq_state->lock);
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+ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
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+ fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
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+ local_fiq_enable();
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+ } else {
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+ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
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+ }
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}
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}
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}
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