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https://github.com/openwrt/openwrt.git
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214 lines
5.7 KiB
Diff
214 lines
5.7 KiB
Diff
From 9a8d3f21c94099a2bcd79ac1684cc8020fd98df2 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
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Date: Mon, 23 Dec 2013 00:32:42 -0300
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Subject: [PATCH] ARM: sun5i: dt: mod0 clocks
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This commit adds all the mod0 clocks available on A10 and A13. The list
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has been constructed by looking at the Allwinner code release for A10S
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and A13.
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Signed-off-by: Emilio López <emilio@elopez.com.ar>
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Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm/boot/dts/sun5i-a10s.dtsi | 88 +++++++++++++++++++++++++++++++++++++++
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arch/arm/boot/dts/sun5i-a13.dtsi | 88 +++++++++++++++++++++++++++++++++++++++
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2 files changed, 176 insertions(+)
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--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
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+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
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@@ -169,6 +169,94 @@
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"apb1_i2c2", "apb1_uart0", "apb1_uart1",
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"apb1_uart2", "apb1_uart3";
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};
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+
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+ nand_clk: clk@01c20080 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c20080 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ clock-output-names = "nand";
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+ };
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+
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+ ms_clk: clk@01c20084 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c20084 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ clock-output-names = "ms";
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+ };
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+
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+ mmc0_clk: clk@01c20088 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c20088 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ clock-output-names = "mmc0";
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+ };
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+
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+ mmc1_clk: clk@01c2008c {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c2008c 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ clock-output-names = "mmc1";
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+ };
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+
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+ mmc2_clk: clk@01c20090 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c20090 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ clock-output-names = "mmc2";
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+ };
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+
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+ ts_clk: clk@01c20098 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c20098 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ clock-output-names = "ts";
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+ };
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+
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+ ss_clk: clk@01c2009c {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c2009c 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ clock-output-names = "ss";
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+ };
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+
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+ spi0_clk: clk@01c200a0 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200a0 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ clock-output-names = "spi0";
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+ };
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+
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+ spi1_clk: clk@01c200a4 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200a4 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ clock-output-names = "spi1";
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+ };
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+
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+ spi2_clk: clk@01c200a8 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200a8 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ clock-output-names = "spi2";
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+ };
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+
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+ ir0_clk: clk@01c200b0 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200b0 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ clock-output-names = "ir0";
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+ };
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};
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soc@01c00000 {
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--- a/arch/arm/boot/dts/sun5i-a13.dtsi
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+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
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@@ -170,6 +170,94 @@
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clock-output-names = "apb1_i2c0", "apb1_i2c1",
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"apb1_i2c2", "apb1_uart1", "apb1_uart3";
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};
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+
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+ nand_clk: clk@01c20080 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c20080 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ clock-output-names = "nand";
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+ };
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+
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+ ms_clk: clk@01c20084 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c20084 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ clock-output-names = "ms";
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+ };
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+
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+ mmc0_clk: clk@01c20088 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c20088 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ clock-output-names = "mmc0";
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+ };
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+
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+ mmc1_clk: clk@01c2008c {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c2008c 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ clock-output-names = "mmc1";
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+ };
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+
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+ mmc2_clk: clk@01c20090 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c20090 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ clock-output-names = "mmc2";
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+ };
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+
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+ ts_clk: clk@01c20098 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c20098 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ clock-output-names = "ts";
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+ };
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+
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+ ss_clk: clk@01c2009c {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c2009c 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ clock-output-names = "ss";
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+ };
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+
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+ spi0_clk: clk@01c200a0 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200a0 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ clock-output-names = "spi0";
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+ };
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+
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+ spi1_clk: clk@01c200a4 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200a4 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ clock-output-names = "spi1";
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+ };
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+
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+ spi2_clk: clk@01c200a8 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200a8 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ clock-output-names = "spi2";
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+ };
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+
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+ ir0_clk: clk@01c200b0 {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c200b0 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ clock-output-names = "ir0";
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+ };
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};
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soc@01c00000 {
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