mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-27 01:11:14 +00:00
47 lines
1.8 KiB
Diff
47 lines
1.8 KiB
Diff
From 3d56b9643ff9fff3c7ceb095e03f4ab7e149b9ce Mon Sep 17 00:00:00 2001
|
|
From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
|
|
Date: Mon, 23 Dec 2013 00:32:34 -0300
|
|
Subject: [PATCH] clk: sunxi: add gating support to PLL1
|
|
MIME-Version: 1.0
|
|
Content-Type: text/plain; charset=UTF-8
|
|
Content-Transfer-Encoding: 8bit
|
|
|
|
This commit adds gating support to PLL1 on the clock driver. This makes
|
|
the PLL1 implementation fully compatible with PLL4 as well.
|
|
|
|
Signed-off-by: Emilio López <emilio@elopez.com.ar>
|
|
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
Acked-by: Mike Turquette <mturquette@linaro.org>
|
|
---
|
|
Documentation/devicetree/bindings/clock/sunxi.txt | 2 +-
|
|
drivers/clk/sunxi/clk-sunxi.c | 2 ++
|
|
2 files changed, 3 insertions(+), 1 deletion(-)
|
|
|
|
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
|
|
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
|
|
@@ -7,7 +7,7 @@ This binding uses the common clock bindi
|
|
Required properties:
|
|
- compatible : shall be one of the following:
|
|
"allwinner,sun4i-osc-clk" - for a gatable oscillator
|
|
- "allwinner,sun4i-pll1-clk" - for the main PLL clock
|
|
+ "allwinner,sun4i-pll1-clk" - for the main PLL clock and PLL4
|
|
"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
|
|
"allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
|
|
"allwinner,sun4i-axi-clk" - for the AXI clock
|
|
--- a/drivers/clk/sunxi/clk-sunxi.c
|
|
+++ b/drivers/clk/sunxi/clk-sunxi.c
|
|
@@ -301,11 +301,13 @@ static struct clk_factors_config sun4i_a
|
|
};
|
|
|
|
static const struct factors_data sun4i_pll1_data __initconst = {
|
|
+ .enable = 31,
|
|
.table = &sun4i_pll1_config,
|
|
.getter = sun4i_get_pll1_factors,
|
|
};
|
|
|
|
static const struct factors_data sun6i_a31_pll1_data __initconst = {
|
|
+ .enable = 31,
|
|
.table = &sun6i_a31_pll1_config,
|
|
.getter = sun6i_a31_get_pll1_factors,
|
|
};
|