mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-27 01:11:14 +00:00
67 lines
1.9 KiB
Diff
67 lines
1.9 KiB
Diff
From 7df19a0adca7806e081479eecb07365652c26ef5 Mon Sep 17 00:00:00 2001
|
|
From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
|
|
Date: Fri, 20 Sep 2013 22:03:12 -0300
|
|
Subject: [PATCH] clk: sunxi: protect core clocks from accidental shutdown
|
|
MIME-Version: 1.0
|
|
Content-Type: text/plain; charset=UTF-8
|
|
Content-Transfer-Encoding: 8bit
|
|
|
|
Some important clocks may get disabled as a side effect of another clock
|
|
being disabled, because they have no consumers. This patch implements a
|
|
mechanism so those clocks can be claimed by the driver and therefore
|
|
remain enabled at all times.
|
|
|
|
Signed-off-by: Emilio López <emilio@elopez.com.ar>
|
|
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
|
|
Conflicts:
|
|
drivers/clk/sunxi/clk-sunxi.c
|
|
---
|
|
drivers/clk/sunxi/clk-sunxi.c | 28 ++++++++++++++++++++++++++++
|
|
1 file changed, 28 insertions(+)
|
|
|
|
--- a/drivers/clk/sunxi/clk-sunxi.c
|
|
+++ b/drivers/clk/sunxi/clk-sunxi.c
|
|
@@ -616,6 +616,31 @@ static void __init of_sunxi_table_clock_
|
|
}
|
|
}
|
|
|
|
+/**
|
|
+ * System clock protection
|
|
+ *
|
|
+ * By enabling these critical clocks, we prevent their accidental gating
|
|
+ * by the framework
|
|
+ */
|
|
+static void __init sunxi_clock_protect(void)
|
|
+{
|
|
+ struct clk *clk;
|
|
+
|
|
+ /* memory bus clock - sun5i+ */
|
|
+ clk = clk_get(NULL, "mbus");
|
|
+ if (!IS_ERR(clk)) {
|
|
+ clk_prepare_enable(clk);
|
|
+ clk_put(clk);
|
|
+ }
|
|
+
|
|
+ /* DDR clock - sun4i+ */
|
|
+ clk = clk_get(NULL, "pll5_ddr");
|
|
+ if (!IS_ERR(clk)) {
|
|
+ clk_prepare_enable(clk);
|
|
+ clk_put(clk);
|
|
+ }
|
|
+}
|
|
+
|
|
static void __init sunxi_init_clocks(struct device_node *np)
|
|
{
|
|
/* Register factor clocks */
|
|
@@ -629,6 +654,9 @@ static void __init sunxi_init_clocks(str
|
|
|
|
/* Register gate clocks */
|
|
of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
|
|
+
|
|
+ /* Enable core system clocks */
|
|
+ sunxi_clock_protect();
|
|
}
|
|
CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sunxi_init_clocks);
|
|
CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sunxi_init_clocks);
|