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https://github.com/openwrt/openwrt.git
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58d2bd88ae
Changes:
- Update patches
- Update dts with new binding
Tx term offset dropped and replaced with a new compatible
Removed:
- 0071-5-PCI-qcom-Programming-the-PCIE-iATU-for-IPQ806x
Pci init does the same exact thing (was needed in older kernel version)
- 0071-7-pcie-Set-PCIE-MRRS-and-MPS-to-256B
Rejected upstream, can't find any reason to have this. No regression with
testing it on R7800.
Tested on R7800 (ipq8065), R7500 v2 ("ipq8064-v2")
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Paul Blazejowski <paulb@blazebox.homeip.net> [R7800]
[rebase and refresh]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
63 lines
2.2 KiB
Diff
63 lines
2.2 KiB
Diff
From ee367e2cdd2202b5714982739e684543cd2cee0e Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Mon, 15 Jun 2020 23:06:00 +0200
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Subject: PCI: qcom: Add missing reset for ipq806x
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Add missing ext reset used by ipq8064 SoC in PCIe qcom driver.
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Link: https://lore.kernel.org/r/20200615210608.21469-5-ansuelsmth@gmail.com
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Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
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Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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Reviewed-by: Rob Herring <robh@kernel.org>
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Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
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Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
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Cc: stable@vger.kernel.org # v4.5+
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---
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drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++
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1 file changed, 12 insertions(+)
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--- a/drivers/pci/controller/dwc/pcie-qcom.c
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+++ b/drivers/pci/controller/dwc/pcie-qcom.c
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@@ -92,6 +92,7 @@ struct qcom_pcie_resources_2_1_0 {
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struct reset_control *ahb_reset;
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struct reset_control *por_reset;
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struct reset_control *phy_reset;
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+ struct reset_control *ext_reset;
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struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
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};
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@@ -261,6 +262,10 @@ static int qcom_pcie_get_resources_2_1_0
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if (IS_ERR(res->por_reset))
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return PTR_ERR(res->por_reset);
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+ res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext");
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+ if (IS_ERR(res->ext_reset))
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+ return PTR_ERR(res->ext_reset);
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+
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res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
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return PTR_ERR_OR_ZERO(res->phy_reset);
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}
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@@ -274,6 +279,7 @@ static void qcom_pcie_deinit_2_1_0(struc
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reset_control_assert(res->axi_reset);
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reset_control_assert(res->ahb_reset);
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reset_control_assert(res->por_reset);
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+ reset_control_assert(res->ext_reset);
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reset_control_assert(res->phy_reset);
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clk_disable_unprepare(res->iface_clk);
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clk_disable_unprepare(res->core_clk);
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@@ -332,6 +338,12 @@ static int qcom_pcie_init_2_1_0(struct q
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goto err_deassert_ahb;
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}
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+ ret = reset_control_deassert(res->ext_reset);
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+ if (ret) {
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+ dev_err(dev, "cannot deassert ext reset\n");
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+ goto err_deassert_ahb;
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+ }
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+
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/* enable PCIe clocks and resets */
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val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
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val &= ~BIT(0);
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