mirror of
https://github.com/openwrt/openwrt.git
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58d2bd88ae
Changes:
- Update patches
- Update dts with new binding
Tx term offset dropped and replaced with a new compatible
Removed:
- 0071-5-PCI-qcom-Programming-the-PCIE-iATU-for-IPQ806x
Pci init does the same exact thing (was needed in older kernel version)
- 0071-7-pcie-Set-PCIE-MRRS-and-MPS-to-256B
Rejected upstream, can't find any reason to have this. No regression with
testing it on R7800.
Tested on R7800 (ipq8065), R7500 v2 ("ipq8064-v2")
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Tested-by: Paul Blazejowski <paulb@blazebox.homeip.net> [R7800]
[rebase and refresh]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
73 lines
2.3 KiB
Diff
73 lines
2.3 KiB
Diff
From dd58318c019f10bc94db36df66af6c55d4c0cbba Mon Sep 17 00:00:00 2001
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From: Abhishek Sahu <absahu@codeaurora.org>
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Date: Mon, 15 Jun 2020 23:05:59 +0200
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Subject: PCI: qcom: Change duplicate PCI reset to phy reset
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The deinit issues reset_control_assert for PCI twice and does not contain
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phy reset.
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Link: https://lore.kernel.org/r/20200615210608.21469-4-ansuelsmth@gmail.com
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Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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Reviewed-by: Rob Herring <robh@kernel.org>
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Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
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---
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drivers/pci/controller/dwc/pcie-qcom.c | 18 ++++++++----------
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1 file changed, 8 insertions(+), 10 deletions(-)
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--- a/drivers/pci/controller/dwc/pcie-qcom.c
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+++ b/drivers/pci/controller/dwc/pcie-qcom.c
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@@ -269,14 +269,14 @@ static void qcom_pcie_deinit_2_1_0(struc
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{
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struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
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+ clk_disable_unprepare(res->phy_clk);
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reset_control_assert(res->pci_reset);
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reset_control_assert(res->axi_reset);
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reset_control_assert(res->ahb_reset);
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reset_control_assert(res->por_reset);
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- reset_control_assert(res->pci_reset);
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+ reset_control_assert(res->phy_reset);
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clk_disable_unprepare(res->iface_clk);
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clk_disable_unprepare(res->core_clk);
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- clk_disable_unprepare(res->phy_clk);
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clk_disable_unprepare(res->aux_clk);
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clk_disable_unprepare(res->ref_clk);
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regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
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@@ -314,12 +314,6 @@ static int qcom_pcie_init_2_1_0(struct q
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goto err_clk_core;
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}
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- ret = clk_prepare_enable(res->phy_clk);
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- if (ret) {
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- dev_err(dev, "cannot prepare/enable phy clock\n");
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- goto err_clk_phy;
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- }
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-
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ret = clk_prepare_enable(res->aux_clk);
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if (ret) {
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dev_err(dev, "cannot prepare/enable aux clock\n");
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@@ -372,6 +366,12 @@ static int qcom_pcie_init_2_1_0(struct q
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return ret;
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}
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+ ret = clk_prepare_enable(res->phy_clk);
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+ if (ret) {
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+ dev_err(dev, "cannot prepare/enable phy clock\n");
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+ goto err_deassert_ahb;
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+ }
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+
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/* wait for clock acquisition */
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usleep_range(1000, 1500);
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@@ -389,8 +389,6 @@ err_deassert_ahb:
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err_clk_ref:
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clk_disable_unprepare(res->aux_clk);
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err_clk_aux:
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- clk_disable_unprepare(res->phy_clk);
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-err_clk_phy:
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clk_disable_unprepare(res->core_clk);
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err_clk_core:
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clk_disable_unprepare(res->iface_clk);
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