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011f2c26f1
As usual these patches were extracted and rebased from the raspberry pi repo: https://github.com/raspberrypi/linux/tree/rpi-4.4.y Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
224 lines
6.7 KiB
Diff
224 lines
6.7 KiB
Diff
From 76359522fa9c449fb715d1933523c153cc1871f3 Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Thu, 29 Sep 2016 10:34:21 -0700
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Subject: [PATCH] drm/vc4: Set up the AVI and SPD infoframes.
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Fixes a purple bar on the left side of the screen with my Dell
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2408WFP. It will also be required for supporting the double-clocked
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video modes.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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---
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drivers/gpu/drm/vc4/vc4_hdmi.c | 136 +++++++++++++++++++++++++++++++++++++++--
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drivers/gpu/drm/vc4/vc4_regs.h | 5 ++
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2 files changed, 136 insertions(+), 5 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -62,6 +62,8 @@ struct vc4_hdmi {
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struct vc4_hdmi_encoder {
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struct vc4_encoder base;
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bool hdmi_monitor;
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+ bool limited_rgb_range;
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+ bool rgb_range_selectable;
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};
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static inline struct vc4_hdmi_encoder *
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@@ -205,6 +207,12 @@ static int vc4_hdmi_connector_get_modes(
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return -ENODEV;
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vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
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+
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+ if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
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+ vc4_encoder->rgb_range_selectable =
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+ drm_rgb_quant_range_selectable(edid);
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+ }
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+
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drm_mode_connector_update_edid_property(connector, edid);
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ret = drm_add_edid_modes(connector, edid);
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@@ -281,6 +289,117 @@ static const struct drm_encoder_funcs vc
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.destroy = vc4_hdmi_encoder_destroy,
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};
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+static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
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+ enum hdmi_infoframe_type type)
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+{
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+ struct drm_device *dev = encoder->dev;
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+ struct vc4_dev *vc4 = to_vc4_dev(dev);
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+ u32 packet_id = type - 0x80;
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+
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+ HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
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+ HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
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+
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+ return wait_for(!(HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) &
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+ BIT(packet_id)), 100);
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+}
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+
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+static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
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+ union hdmi_infoframe *frame)
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+{
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+ struct drm_device *dev = encoder->dev;
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+ struct vc4_dev *vc4 = to_vc4_dev(dev);
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+ u32 packet_id = frame->any.type - 0x80;
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+ u32 packet_reg = VC4_HDMI_GCP_0 + VC4_HDMI_PACKET_STRIDE * packet_id;
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+ uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
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+ ssize_t len, i;
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+ int ret;
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+
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+ WARN_ONCE(!(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
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+ VC4_HDMI_RAM_PACKET_ENABLE),
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+ "Packet RAM has to be on to store the packet.");
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+
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+ len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
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+ if (len < 0)
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+ return;
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+
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+ ret = vc4_hdmi_stop_packet(encoder, frame->any.type);
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+ if (ret) {
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+ DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
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+ return;
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+ }
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+
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+ for (i = 0; i < len; i += 7) {
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+ HDMI_WRITE(packet_reg,
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+ buffer[i + 0] << 0 |
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+ buffer[i + 1] << 8 |
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+ buffer[i + 2] << 16);
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+ packet_reg += 4;
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+
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+ HDMI_WRITE(packet_reg,
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+ buffer[i + 3] << 0 |
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+ buffer[i + 4] << 8 |
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+ buffer[i + 5] << 16 |
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+ buffer[i + 6] << 24);
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+ packet_reg += 4;
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+ }
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+
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+ HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
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+ HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
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+ ret = wait_for((HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) &
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+ BIT(packet_id)), 100);
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+ if (ret)
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+ DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
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+}
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+
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+static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
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+{
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+ struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
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+ struct drm_crtc *crtc = encoder->crtc;
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+ const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
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+ union hdmi_infoframe frame;
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+ int ret;
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+
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+ ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode);
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+ if (ret < 0) {
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+ DRM_ERROR("couldn't fill AVI infoframe\n");
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+ return;
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+ }
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+
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+ if (vc4_encoder->rgb_range_selectable) {
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+ if (vc4_encoder->limited_rgb_range) {
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+ frame.avi.quantization_range =
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+ HDMI_QUANTIZATION_RANGE_LIMITED;
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+ } else {
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+ frame.avi.quantization_range =
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+ HDMI_QUANTIZATION_RANGE_FULL;
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+ }
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+ }
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+
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+ vc4_hdmi_write_infoframe(encoder, &frame);
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+}
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+
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+static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
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+{
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+ union hdmi_infoframe frame;
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+ int ret;
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+
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+ ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
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+ if (ret < 0) {
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+ DRM_ERROR("couldn't fill SPD infoframe\n");
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+ return;
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+ }
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+
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+ frame.spd.sdi = HDMI_SPD_SDI_PC;
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+
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+ vc4_hdmi_write_infoframe(encoder, &frame);
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+}
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+
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+static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
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+{
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+ vc4_hdmi_set_avi_infoframe(encoder);
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+ vc4_hdmi_set_spd_infoframe(encoder);
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+}
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+
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static void vc4_hdmi_encoder_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *unadjusted_mode,
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struct drm_display_mode *mode)
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@@ -349,8 +468,9 @@ static void vc4_hdmi_encoder_mode_set(st
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if (vc4_encoder->hdmi_monitor && drm_match_cea_mode(mode) > 1) {
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/* CEA VICs other than #1 requre limited range RGB
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- * output. Apply a colorspace conversion to squash
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- * 0-255 down to 16-235. The matrix here is:
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+ * output unless overridden by an AVI infoframe.
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+ * Apply a colorspace conversion to squash 0-255 down
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+ * to 16-235. The matrix here is:
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*
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* [ 0 0 0.8594 16]
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* [ 0 0.8594 0 16]
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@@ -368,6 +488,9 @@ static void vc4_hdmi_encoder_mode_set(st
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HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000);
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HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0);
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HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000);
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+ vc4_encoder->limited_rgb_range = true;
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+ } else {
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+ vc4_encoder->limited_rgb_range = false;
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}
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/* The RGB order applies even when CSC is disabled. */
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@@ -386,6 +509,8 @@ static void vc4_hdmi_encoder_disable(str
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struct drm_device *dev = encoder->dev;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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+ HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 0);
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+
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HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
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HD_WRITE(VC4_HD_VID_CTL,
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HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
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@@ -438,9 +563,10 @@ static void vc4_hdmi_encoder_enable(stru
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HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
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VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
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- /* XXX: Set HDMI_RAM_PACKET_CONFIG (1 << 16) and set
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- * up the infoframe.
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- */
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+ HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
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+ VC4_HDMI_RAM_PACKET_ENABLE);
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+
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+ vc4_hdmi_set_infoframes(encoder);
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drift = HDMI_READ(VC4_HDMI_FIFO_CTL);
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drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
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--- a/drivers/gpu/drm/vc4/vc4_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_regs.h
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@@ -443,6 +443,8 @@
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#define VC4_HDMI_RAM_PACKET_CONFIG 0x0a0
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# define VC4_HDMI_RAM_PACKET_ENABLE BIT(16)
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+#define VC4_HDMI_RAM_PACKET_STATUS 0x0a4
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+
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#define VC4_HDMI_HORZA 0x0c4
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# define VC4_HDMI_HORZA_VPOS BIT(14)
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# define VC4_HDMI_HORZA_HPOS BIT(13)
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@@ -504,6 +506,9 @@
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#define VC4_HDMI_TX_PHY_RESET_CTL 0x2c0
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+#define VC4_HDMI_GCP_0 0x400
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+#define VC4_HDMI_PACKET_STRIDE 0x24
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+
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#define VC4_HD_M_CTL 0x00c
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# define VC4_HD_M_REGISTER_FILE_STANDBY (3 << 6)
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# define VC4_HD_M_RAM_STANDBY (3 << 4)
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