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5b089e45a6
Refresh patches on all 4.4 supported platforms. Compile & run tested: lantiq/xrx200 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
88 lines
2.5 KiB
Diff
88 lines
2.5 KiB
Diff
From 105aa2411add3d0d8bb815109e4a6fb6c778a1d2 Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Thu, 14 Apr 2016 19:00:33 -0700
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Subject: [PATCH] clk: bcm2835: Add an enum for the DSI1 pixel clock.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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---
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drivers/clk/bcm/clk-bcm2835.c | 39 +++++++++++++++++++++++++++++++++++--
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include/dt-bindings/clock/bcm2835.h | 1 +
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2 files changed, 38 insertions(+), 2 deletions(-)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -936,6 +936,9 @@ static long bcm2835_clock_rate_from_divi
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const struct bcm2835_clock_data *data = clock->data;
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u64 temp;
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+ if (data->int_bits == 0 && data->frac_bits == 0)
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+ return parent_rate;
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+
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/*
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* The divisor is a 12.12 fixed point field, but only some of
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* the bits are populated in any given clock.
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@@ -959,7 +962,12 @@ static unsigned long bcm2835_clock_get_r
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struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
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struct bcm2835_cprman *cprman = clock->cprman;
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const struct bcm2835_clock_data *data = clock->data;
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- u32 div = cprman_read(cprman, data->div_reg);
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+ u32 div;
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+
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+ if (data->int_bits == 0 && data->frac_bits == 0)
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+ return parent_rate;
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+
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+ div = cprman_read(cprman, data->div_reg);
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return bcm2835_clock_rate_from_divisor(clock, parent_rate, div);
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}
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@@ -1405,6 +1413,28 @@ static const char *const bcm2835_clock_v
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__VA_ARGS__)
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/*
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+ * DSI1 parent clocks. The DSI1 byte clock comes from the DSI1 PHY,
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+ * which in turn sources from plld_dsi1.
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+ */
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+static const char *const bcm2835_clock_dsi1_parents[] = {
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+ "gnd",
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+ "xosc",
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+ "testdebug0",
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+ "testdebug1",
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+ "dsi1_ddr",
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+ "dsi1_ddr_inv",
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+ "dsi1_ddr2",
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+ "dsi1_ddr2_inv",
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+ "dsi1_byte",
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+ "dsi1_byte_inv",
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+};
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+
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+#define REGISTER_DSI1_CLK(...) REGISTER_CLK( \
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+ .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents), \
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+ .parents = bcm2835_clock_dsi1_parents, \
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+ __VA_ARGS__)
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+
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+/*
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* the real definition of all the pll, pll_dividers and clocks
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* these make use of the above REGISTER_* macros
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*/
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@@ -1849,7 +1879,12 @@ static const struct bcm2835_clk_desc clk
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.div_reg = CM_DSI1EDIV,
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.int_bits = 4,
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.frac_bits = 8),
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-
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+ [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK(
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+ .name = "dsi1p",
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+ .ctl_reg = CM_DSI1PCTL,
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+ .div_reg = CM_DSI1PDIV,
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+ .int_bits = 0,
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+ .frac_bits = 0),
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/* the gates */
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/*
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--- a/include/dt-bindings/clock/bcm2835.h
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+++ b/include/dt-bindings/clock/bcm2835.h
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@@ -64,3 +64,4 @@
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#define BCM2835_CLOCK_CAM1 46
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#define BCM2835_CLOCK_DSI0E 47
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#define BCM2835_CLOCK_DSI1E 48
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+#define BCM2835_CLOCK_DSI1P 49
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