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5b089e45a6
Refresh patches on all 4.4 supported platforms. Compile & run tested: lantiq/xrx200 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
41 lines
1.3 KiB
Diff
41 lines
1.3 KiB
Diff
From 817850fa2ab1a1b66ac1235b9dfe403d5efc8ac4 Mon Sep 17 00:00:00 2001
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From: Martin Sperl <kernel@martin.sperl.org>
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Date: Mon, 29 Feb 2016 12:51:43 +0000
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Subject: [PATCH] clk: bcm2835: enable management of PCM clock
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Enable the PCM clock in the SOC, which is used by the
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bcm2835-i2s driver.
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Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Reviewed-by: Eric Anholt <eric@anholt.net>
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(cherry picked from commit 33b689600f43094a9316a1b582f2286d17bc737b)
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---
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drivers/clk/bcm/clk-bcm2835.c | 7 +++++++
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include/dt-bindings/clock/bcm2835.h | 1 +
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2 files changed, 8 insertions(+)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -1640,6 +1640,13 @@ static const struct bcm2835_clk_desc clk
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.div_reg = CM_HSMDIV,
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.int_bits = 4,
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.frac_bits = 8),
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+ [BCM2835_CLOCK_PCM] = REGISTER_PER_CLK(
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+ .name = "pcm",
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+ .ctl_reg = CM_PCMCTL,
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+ .div_reg = CM_PCMDIV,
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+ .int_bits = 12,
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+ .frac_bits = 12,
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+ .is_mash_clock = true),
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[BCM2835_CLOCK_PWM] = REGISTER_PER_CLK(
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.name = "pwm",
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.ctl_reg = CM_PWMCTL,
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--- a/include/dt-bindings/clock/bcm2835.h
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+++ b/include/dt-bindings/clock/bcm2835.h
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@@ -44,3 +44,4 @@
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#define BCM2835_CLOCK_EMMC 28
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#define BCM2835_CLOCK_PERI_IMAGE 29
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#define BCM2835_CLOCK_PWM 30
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+#define BCM2835_CLOCK_PCM 31
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