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029093a302
This target has full device tree support, thus reducing the number of patches needed for bcm63xx, in which there's a patch for every board. The intention is to start with a minimal amount of downstream patches and start upstreaming all of them. Current status: - Enabling EHCI/OHCI on BCM6358 causes a kernel panic. - BCM63268 lacks Timer Clocks/Reset support. - No PCI/PCIe drivers. - No ethernet drivers. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
69 lines
2.2 KiB
C
69 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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#ifndef __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6328_H
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#define __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6328_H
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#define BCM6328_IRQ_NAND 0
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#define BCM6328_IRQ_PCM 1
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#define BCM6328_IRQ_PCM_DMA0 2
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#define BCM6328_IRQ_PCM_DMA1 3
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#define BCM6328_IRQ_USBS 4
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#define BCM6328_IRQ_USB_CTL_RX_DMA 5
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#define BCM6328_IRQ_USB_CTL_TX_DMA 6
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#define BCM6328_IRQ_USB_BULK_RX_DMA 7
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#define BCM6328_IRQ_USB_BULK_TX_DMA 8
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#define BCM6328_IRQ_USB_ISO_RX_DMA 9
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#define BCM6328_IRQ_USB_ISO_TX_DMA 10
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#define BCM6328_IRQ_DG 11
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#define BCM6328_IRQ_EPHY 12
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#define BCM6328_IRQ_EPHY_EN0N 13
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#define BCM6328_IRQ_EPHY_EN1N 14
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#define BCM6328_IRQ_EPHY_EN2N 15
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#define BCM6328_IRQ_EPHY_EN3N 16
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#define BCM6328_IRQ_EPHY_EN0 17
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#define BCM6328_IRQ_EPHY_EN1 18
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#define BCM6328_IRQ_EPHY_EN2 19
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#define BCM6328_IRQ_EPHY_EN3 20
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#define BCM6328_IRQ_XDSL 21
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#define BCM6328_IRQ_PCIE_EP 22
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#define BCM6328_IRQ_PCIE_RC 23
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#define BCM6328_IRQ_EXTO 24
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#define BCM6328_IRQ_EXT1 25
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#define BCM6328_IRQ_EXT2 26
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#define BCM6328_IRQ_EXT3 27
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#define BCM6328_IRQ_UART0 28
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#define BCM6328_IRQ_HSSPI 29
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#define BCM6328_IRQ_WAKE_ON_IRQ 30
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#define BCM6328_IRQ_TIMER 31
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#define BCM6328_IRQ_ENETSW_RX_DMA0 32
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#define BCM6328_IRQ_ENETSW_RX_DMA1 33
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#define BCM6328_IRQ_ENETSW_TX_DMA0 34
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#define BCM6328_IRQ_ENETSW_TX_DMA1 35
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#define BCM6328_IRQ_UART1 39
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#define BCM6328_IRQ_ENETSW 40
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#define BCM6328_IRQ_OHCI 41
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#define BCM6328_IRQ_EHCI 42
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#define BCM6328_IRQ_ATM_DMA0 43
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#define BCM6328_IRQ_ATM_DMA1 44
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#define BCM6328_IRQ_ATM_DMA2 45
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#define BCM6328_IRQ_ATM_DMA3 46
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#define BCM6328_IRQ_ATM_DMA4 47
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#define BCM6328_IRQ_ATM_DMA5 48
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#define BCM6328_IRQ_ATM_DMA6 49
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#define BCM6328_IRQ_ATM_DMA7 50
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#define BCM6328_IRQ_ATM_DMA8 51
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#define BCM6328_IRQ_ATM_DMA9 52
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#define BCM6328_IRQ_ATM_DMA10 53
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#define BCM6328_IRQ_ATM_DMA11 54
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#define BCM6328_IRQ_ATM_DMA12 55
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#define BCM6328_IRQ_ATM_DMA13 56
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#define BCM6328_IRQ_ATM_DMA14 57
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#define BCM6328_IRQ_ATM_DMA15 58
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#define BCM6328_IRQ_ATM_DMA16 59
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#define BCM6328_IRQ_ATM_DMA17 60
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#define BCM6328_IRQ_ATM_DMA18 61
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#define BCM6328_IRQ_ATM_DMA19 62
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#define BCM6328_IRQ_SAR 63
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#endif /* __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6328_H */
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