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105 lines
3.6 KiB
Diff
105 lines
3.6 KiB
Diff
From patchwork Tue Nov 8 14:59:01 2011
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: MIPS: Kernel hangs occasionally during boot.
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Date: Tue, 08 Nov 2011 13:59:01 -0000
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From: Al Cooper <alcooperx@gmail.com>
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X-Patchwork-Id: 2911
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Message-Id: <1320764341-4275-1-git-send-email-alcooperx@gmail.com>
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To: ralf@linux-mips.org, linux-mips@linux-mips.org,
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linux-kernel@vger.kernel.org
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Cc: "Al Cooper" <alcooperx@gmail.com>
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The Kernel hangs occasionally during boot after
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"Calibrating delay loop..". This is caused by the
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c0_compare_int_usable() routine in cevt-r4k.c returning false which
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causes the system to disable the timer and hang later. The false
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return happens because the routine is using a series of four calls to
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irq_disable_hazard() as a delay while it waits for the timer changes
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to propagate to the cp0 cause register. On newer MIPS cores, like the 74K,
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the series of irq_disable_hazard() calls turn into ehb instructions and
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can take as little as a few clock ticks for all 4 instructions. This
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is not enough of a delay, so the routine thinks the timer is not working.
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This fix uses up to a max number of cycle counter ticks for the delay
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and uses back_to_back_c0_hazard() instead of irq_disable_hazard() to
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handle the hazard condition between cp0 writes and cp0 reads.
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Signed-off-by: Al Cooper <alcooperx@gmail.com>
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---
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arch/mips/kernel/cevt-r4k.c | 38 +++++++++++++++++++-------------------
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1 files changed, 19 insertions(+), 19 deletions(-)
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--- a/arch/mips/kernel/cevt-r4k.c
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+++ b/arch/mips/kernel/cevt-r4k.c
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@@ -103,19 +103,10 @@ static int c0_compare_int_pending(void)
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/*
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* Compare interrupt can be routed and latched outside the core,
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- * so a single execution hazard barrier may not be enough to give
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- * it time to clear as seen in the Cause register. 4 time the
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- * pipeline depth seems reasonably conservative, and empirically
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- * works better in configurations with high CPU/bus clock ratios.
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+ * so wait up to worst case number of cycle counter ticks for timer interrupt
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+ * changes to propagate to the cause register.
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*/
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-
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-#define compare_change_hazard() \
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- do { \
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- irq_disable_hazard(); \
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- irq_disable_hazard(); \
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- irq_disable_hazard(); \
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- irq_disable_hazard(); \
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- } while (0)
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+#define COMPARE_INT_SEEN_TICKS 50
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int c0_compare_int_usable(void)
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{
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@@ -126,8 +117,12 @@ int c0_compare_int_usable(void)
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* IP7 already pending? Try to clear it by acking the timer.
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*/
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if (c0_compare_int_pending()) {
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- write_c0_compare(read_c0_count());
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- compare_change_hazard();
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+ cnt = read_c0_count();
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+ write_c0_compare(cnt);
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+ back_to_back_c0_hazard();
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+ while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
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+ if (!c0_compare_int_pending())
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+ break;
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if (c0_compare_int_pending())
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return 0;
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}
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@@ -136,7 +131,7 @@ int c0_compare_int_usable(void)
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cnt = read_c0_count();
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cnt += delta;
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write_c0_compare(cnt);
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- compare_change_hazard();
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+ back_to_back_c0_hazard();
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if ((int)(read_c0_count() - cnt) < 0)
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break;
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/* increase delta if the timer was already expired */
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@@ -145,12 +140,17 @@ int c0_compare_int_usable(void)
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while ((int)(read_c0_count() - cnt) <= 0)
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; /* Wait for expiry */
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- compare_change_hazard();
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+ while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
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+ if (c0_compare_int_pending())
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+ break;
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if (!c0_compare_int_pending())
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return 0;
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-
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- write_c0_compare(read_c0_count());
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- compare_change_hazard();
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+ cnt = read_c0_count();
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+ write_c0_compare(cnt);
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+ back_to_back_c0_hazard();
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+ while (read_c0_count() < (cnt + COMPARE_INT_SEEN_TICKS))
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+ if (!c0_compare_int_pending())
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+ break;
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if (c0_compare_int_pending())
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return 0;
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